8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Automotive DDR4 SDRAM
MT40A1G8
MT40A512M16
1
Options Marking
Features
Configuration
V = V = 1.2V 60mV
DD DDQ
1 Gig x 8 1G8
V = 2.5V 125mV/+250mV
PP
512 Meg x 16 512M16
On-die, internal, adjustable V generation
REFDQ
78-ball FBGA package (Pb-free) x8
1.2V pseudo open-drain I/O
8mm x 12mm Rev. B WE
Refresh time of 8192-cycle at T temperature range:
C
7.5mm x 11mm Rev. E SA
64ms at 40C to 85C
96-ball FBGA package (Pb-free) x16
32ms at 85C to 95C
8mm x 14mm Rev. B JY
16ms at 95C to 105C
7.5mm x 13.5mm Rev. E LY
8ms at 105C to 125C
Timing cycle time
16 internal banks (x8): 4 groups of 4 banks each
0.625ns @ CL = 22 (DDR4-3200) -062E
8 internal banks (x16): 2 groups of 4 banks each
0.750ns @ CL = 18 (DDR4-2666) -075E
8n-bit prefetch architecture
0.833ns @ CL = 16 (DDR4-2400) -083E
Programmable data strobe preambles
Product certification
Data strobe preamble training
Automotive A
Command/Address latency (CAL)
Operating temperature
Multipurpose register read and write capability
Industrial (40 T 95C) IT
C
Write leveling
Automotive (40 T 105C) AT
C
Self refresh mode
3
Ultra-high (40 T 125C) UT
C
Low-power auto self refresh (LPASR)
Revision :B, :E
Temperature controlled refresh (TCR)
1. Not all options listed can be combined to
Notes:
Fine granularity refresh
define an offered product. Use the part
Self refresh abort
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Features
Table 1: Key Timing Parameters
1 t t t
Speed Grade Data Rate (MT/s) Target CL-nRCD-nRP AA (ns) RCD (ns) RP (ns)
-062E 3200 22-22-22 13.75 13.75 13.75
-075E 2666 18-18-18 13.5 13.5 13.5
-083E 2400 16-16-16 13.32 13.32 13.32
Note: 1. Refer to the Speed Bin Tables for backward compatibility.
Table 2: Addressing
Parameter 1024 Meg x 8 512 Meg x 16
Number of bank groups 4 2
Bank group address BG[1:0] BG0
Bank count per group 4 4
Bank address in bank group BA[1:0] BA[1:0]
Row addressing 64K (A[15:0]) 64K (A[15:0])
Column addressing 1K (A[9:0]) 1K (A[9:0])
1
Page size 1KB 2KB
Note: 1. Page size is per bank, calculated as follows:
COLBITS
Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
Figure 1: Order Part Number Example
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8gb_auto_ddr4_dram.pdf - Rev. G 08/19 EN 2016 Micron Technology, Inc. All rights reserved.
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