MT41K256M8DA-125 IT:K TR Micron

2Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks Automatic self refresh (ASR) Description Write leveling The 1.35V DDR3L SDRAM device is a low-voltage ver- Multipurpose register sion of the 1.5V DDR3 SDRAM device. Refer to the Output driver calibration DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V compatible mode. Options Marking Configuration Features 512 Meg x 4 512M4 V = V = 1.35V (1.2831.45V) DD DDQ 256 Meg x 8 256M8 Backward-compatible to V = V = 1.5V 0.075V DD DDQ 128 Meg x 16 128M16 Differential bidirectional data strobe FBGA package (Pb-free) x4, x8 8n-bit prefetch architecture 78-ball (8mm x 10.5mm x 1.2mm) Differential clock inputs (CK, CK#) DA Rev. K 8 internal banks FBGA package (Pb-free) x16 Nominal and dynamic on-die termination (ODT) 96-ball (8mm x 14mm x 1.2mm) JT for data, strobe, and mask signals Rev. K Programmable CAS (READ) latency (CL) Timing cycle time Programmable posted CAS additive latency (AL) 1.07ns @ CL = 13 (DDR3-1866) -107 Programmable CAS (WRITE) latency (CWL) 1.25ns @ CL = 11 (DDR3-1600) -125 Fixed burst length (BL) of 8 and burst chop (BC) of 4 1.5ns @ CL = 9 (DDR3-1333) -15E (via the mode register set [MRS]) 1.875ns @ CL = 7 (DDR3-1066) -187E Selectable BC4 or BL8 on-the-fly (OTF) Operating temperature Self refresh mode Commercial (0C T +95C) None C T of 95C C Industrial (40C T +95C) IT C 64ms, 8192-cycle refresh up to 85C Revision :K 32ms, 8192-cycle refresh at >85C to 95C Self refresh temperature (SRT) Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 1, 2, 3 -107 1866 13-13-13 13.91 13.91 13.91 1, 2 -125 1600 11-11-11 13.75 13.75 13.75 1 -15E 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 1. Backward compatible to 1066, CL = 7 (-187E). Notes: 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-125). CCMTD-1725822587-7895 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 2Gb_DDR3L.pdf - Rev. O 09/18 EN 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 32K A[14:0] 32K A[14:0] 16K A[13:0] Bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0] Column address 2K A[11, 9:0] 1K A[9:0] 1K A[9:0] Figure 1: DDR3L Part Numbers Example Part Number: MT41K256M8DA-107:K - : MT41K Configuration Package Speed Revision :K Revision Configuration 512 Meg x 4 512M4 Temperature 256 Meg x 8 256M8 Commercial None 128 Meg x 16 128M16 Industrial temperature IT Package Speed Grade t 78-ball 8mm x 10.5mm FBGA -107 DA CK = 1.071ns, CL = 13 t 96-ball 8mm x 14mm FBGA JT -125 CK = 1.25ns, CL = 11 t -15E CK = 1.5ns, CL = 9 t -187E CK = 1.87ns, CL = 7 Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on