MT49H32M18CBM-18:B Micron

576Mb: x9, x18 SIO RLDRAM 2 Features SIO RLDRAM 2 MT49H32M18C 32 Meg x 18 x 8 banks MT49H64M9C 64 Meg x 9 x 8 banks 1 Options Marking Features Clock cycle timing 533 MHz DDR operation (1.067 Gb/s/pin data rate) t 1.875ns @ RC = 15ns -18 t 38.4 Gb/s peak bandwidth (x18 at 533 MHz clock 2.5ns @ RC = 15ns -25E t frequency) 2.5ns @ RC = 20ns -25 t Organization 3.3ns @ RC = 20ns -33 32 Meg x 18 and 64 Meg x 9 separate I/O Configuration 8 banks 64 Meg x 9 64M9 32 Meg x 18 32M18 Reduced cycle time (15ns at 533 MHz) Operating temperature range Nonmultiplexed addresses (address multiplexing Commercial (0 to +95C) None option available) Industrial (T = 40C to +95C; IT C SRAM-type interface T = 40C to +85C) A Programmable READ latency (RL), row cycle time, Package and burst sequence length 144-ball BGA FM Balanced READ and WRITE latencies in order to op- 144-ball BGA (Pb-free) BM timize data bus utilization 144-ball FBGA TR Data mask for WRITE commands 144-ball FBGA (Pb-free) SJ Revision :A/:B Differential input clocks (CK, CK#) Differential input data clocks (DKx, DKx#) Note: 1. Not all options listed can be combined to define an offered product. Use the part cat- On-die DLL generates CK edge-aligned data and alog search on www.micron.com for availa- output data clock signals ble offerings. Data valid signal (QVLD) 32ms refresh (16K refresh for each bank; 128K re- fresh command must be issued in total each 32ms) HSTL I/O (1.5V or 1.8V nominal) matched impedance outputs 2.5V V , 1.8V V , 1.5V or 1.8V V I/O EXT DD DDQ On-die termination (ODT) R TT PDF: 09005aef815b2df8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 576Mb_RLDRAM_2_SIO.pdf - Rev. J 09/15 EN 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.576Mb: x9, x18 SIO RLDRAM 2 Features Figure 1: Part Numbers Example Part Number: MT49H32M18CSJ-25 :B -: MT49H Configuration I/O Package Speed Temp Rev. Revision I/O Common None Rev. A None Separate C Rev. B :B Temperature Configuration Commercial None 64 Meg x 9 64M9 Industrial IT 32 Meg x 18 32M18 Package Speed Grade t 144-ball BGA FM -18 CK = 1.8ns t 144-ball BGA (Pb-free) BM -25 CK = 2.5ns t 144-ball FBGA TR -25E CK = 2.5ns t -33 144-ball FBGA (Pb-free) SJ CK = 3.3ns BGA Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Microns BGA Part Marking Decoder is available on Microns Web site at www.micron.com. PDF: 09005aef815b2df8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 576Mb_RLDRAM_2_SIO.pdf - Rev. J 09/15 EN 2015 Micron Technology, Inc. All rights reserved.