74HCT27PW Nexperia

74HC27 74HCT27 Triple 3-input NOR gate Rev. 4 5 June 2013 Product data sheet 1. General description The 74HC27 74HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC27: CMOS level For 74HCT27: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC27N 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74HCT27N 74HC27D 40 C to +125 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74HCT27D 74HC27DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body width SOT337-1 5.3 mm 74HCT27DB 74HC27PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads body SOT402-1 width 4.4 mm 74HCT27PW 74HC27BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package no leads 14 terminals 74HCT27BQ body 2.5 3 0.85 mm&& 74HC27 74HCT27 NXP Semiconductors Triple 3-input NOR gate 4. Functional diagram 1 1 2 12 1 1A 13 2 1B 1Y 12 13 1C 3 1 3 2A 4 6 4 2B 2Y 6 5 5 2C A 9 3A 9 1 10 3B 3Y 8 10 8 Y B 11 3C 11 C mna936 mna935 mna937 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning +& +&7 74HC27 WHUPLQDO 74HCT27 9 LQGH DUHD % & 1A 1 14 V CC < 1B 2 13 1C % & 2A 3 12 1Y 2B 4 11 3C & % *1 2C 5 10 3B < 2Y 6 9 3A GND 7 8 3Y DDD 001aag759 WYRZDW U (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP14, SO14, (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74HC HCT27 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 5 June 2013 2 of 17 *1 < 7UDQHQVSLHS