74LV132BQ NXP

74LV132 Quad 2-input NAND Schmitt trigger Rev. 05 2 July 2009 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply dened, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is dened as the T+ T- input hysteresis voltage V . H 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Applications n Wave and pulse shapers for highly noisy environments n Astable multivibrators n Monostable multivibrators74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV132N - 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74LV132D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV132DB - 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV132PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV132BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm 5. Functional diagram 1A 1 1Y 3 1B 2 1 & 3 2 2A 4 2Y 4 6 & 6 2B 5 5 9 3A & 8 9 10 3Y 8 3B 12 10 & 11 13 4A 12 A mna408 4Y 11 Y 4B 13 B mna407 mna409 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LV132 5 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 2 July 2009 2 of 17