Freescale Semiconductor Document Number: BSC9132 Data Sheet: Technical Data Rev. 1, 08/2014 BSC9132 BSC9132 QorIQ Qonverge Multicore Baseband FC-PBGA780 23 mm x 23 mm Processor The following list provides an overview of the feature set: TCP/IP acceleration, quality of service, and classification capabilities Two high-performance 32-bit e500 cores built on Power IEEE Std 1588 support Architecture technology: Supports SGMII interfaces 36-bit physical addressing High-speed interfaces supporting the following Double-precision floating-point support multiplexing options: 32-Kbyte L1 instruction cache and 32-Kbyte L1 data One PCI Express interface with 5G support cache Four lanes of high-speed serial interfaces (SerDes) to be Enhanced hardware and software debug support shared between PCI Express, SGMII, and CPRI 800 Mhz/1 GHz/1.2 GHz clock frequency High-speed USB controller (USB 2.0) 512-Kbyte L2 cache with ECC also configurable as Host and device support SRAM and stashing memory Enhanced host controller interface (EHCI) Two SC3850 core subsystems each core connects to the ULPI interface following: Enhanced secure digital (SD/MMC) host controller 32 Kbyte 8-way level 1 data/instruction cache (eSDHC) (L1 Dcache/ICache) Integrated Flash controller (IFC), supporting NAND, 512 Kbyte 8-way level 2 unified instruction/data cache NOR, and general ASIC (L2 cache/M2 memory) Two TDM interfaces Memory management unit (MMU) Antenna interface controller (AIC), supporting four Enhanced programmable interrupt controller (EPIC) industry standard JESD/four custom parallel RF interfaces Debug and profiling unit (DPU) (three dual and one single port) and a 2-lane CPRI interface Two 32-bit quad timers Universal Subscriber Identity Module (USIM) interface 32 Kbytes of shared M3 memory Facilitates communication to SIM cards or Eurochip Multi Accelerator Platform Engine for Pico Base Station pre-paid phone cards Baseband Processing (MAPLE-B2P) Two enhanced serial peripheral interfaces (eSPI) Supports variable sizes in Fourier Transforms, Programmable interrupt controller (PIC) compliant with Convolution, Filtering, Turbo, Viterbi, Chiprate, MIMO OpenPIC standard Consists of accelerators for UMTS chip rate processing, Two DMA controllers LTE UP/DL channel processing, Matrix Inversion 4-channel DMA on Power Architecture side operations, and CRC algorithms 32 unidirectional channels, providing up to 16 Two DDR3/DDR3L SDRAM memory controllers support memory-to-memory channels on DSP side 32-bit with ECC 2 Two I C interfaces Integrated security engine (ULE CAAM) Two dual UART (DUART) interfaces Protocol support includes DES, AES, RNG, CRC, MDE, 96 general-purpose I/O signals PKE, SHA, and MD5 Eight 32-bit timers Secure boot capability Operating temperature (Ta - T ) range: 0105 C Two enhanced three-speed Ethernet controllers (eTSECs) j 2014 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments 3 2.22 Universal Subscriber Identity Module (USIM) 123 1.1 Ball Layout Diagrams .4 2.23 Timers and Timers 32b AC Timing Specifications 127 1.2 Pinout Assignments 8 3 Hardware Design Considerations 128 2 Electrical Characteristics 53 3.1 Power Architecture System Clocking . 128 2.1 Overall DC Electrical Characteristics 53 3.2 DSP System Clocking 131 2.2 Power Sequencing 57 3.3 Supply Power Default Setting 132 2.3 Power-Down Requirements .59 3.4 PLL Power Supply Design . 133 2.4 RESET Initialization .59 3.5 Decoupling Recommendations . 134 2.5 Power-on Ramp Rate 59 3.6 SerDes Block Power Supply Decoupling 2.6 Power Characteristics 60 Recommendations . 135 2.7 Input Clocks .61 3.7 Guidelines for High-Speed Interface Termination . 136 2.8 DDR3 and DDR3L SDRAM Controller .64 3.8 Pull-Up and Pull-Down Resistor Requirements . 136 2.9 eSPI .73 3.9 Output Buffer DC Impedance 137 2.10 DUART .75 3.10 Configuration Pin Muxing . 137 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .76 3.11 JTAG Configuration Signals 138 2.12 USB 81 3.12 Guidelines for High-Speed Interface Termination . 140 2.13 Integrated Flash Controller (IFC) .83 3.13 Thermal . 140 2.14 Enhanced Secure Digital Host Controller (eSDHC) .87 3.14 Security Fuse Processor 141 2.15 Programmable Interrupt Controller (PIC) Specifications89 4 Package Information 141 2.16 JTAG .92 4.1 Package Parameters . 141 2 2.17 I C .94 4.2 Mechanical Dimensions of the FC-PBGA . 142 2.18 GPIO .96 5 Ordering Information 143 2.19 TDM .98 5.1 Part Marking . 143 2.20 High-Speed Serial Interface (HSSI) DC Electrical 6 Product Documentation 143 Characteristics 101 7 Revision History . 144 2.21 Radio Frequency (RF) Interface .120 BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1 2 Freescale Semiconductor