CBTL05024BSHP NXP

CBTL05024 High performance multiplexer/demultiplexer switch for Thunderbolt applications Rev. 4 27 March 2014 Product data sheet 1. General description The CBTL05024 is a multiplexer/demultiplexer switch chip optimized to interface the Thunderbolt/MiniDP connector with Thunderbolt systems. It supports 10.3125 Gbit/s Thunderbolt or DisplayPort v1.2 channels. The TB MUX is a 3 : 1 switch that selects between Thunderbolt data path and DisplayPort v1.2 side-band signals either DDC or AUX. The DP MUX is a 2 : 1 switch that selects between DP ML (DisplayPort Main Link) and LS TX/RX signals. Both LSTX and LSRX are the side-band signals for Thunderbolt channel. This chip also includes HPD and CA DET buffers for HPD IN and CA DET control signals. CBTL05024 is powered by a 3.3 V supply and it is available in a 3 mm 3 mm HVQFN24 package with 0.4 mm pitch. 2. Features and benefits 2.1 TB MUX 3 : 1 switch This 3 : 1 switch is implemented by two cascaded 2 : 1 switches The first 2 : 1 10G MUX is controlled by TB ENA, AUXIO EN and DP PD pins The second 2 : 1 AUX MUX is controlled by CA DET signal multiplexing of the 720 Mbit/s Differential FAUX (or 1 Mbit/s AUX) and DDC (Direct Display Control) signals When CA DET is HIGH, DDC path is selected Differential TB channel Low insertion loss: 1.3 dB at 5 GHz Low return loss: < 20 dB at 5 GHz Low ON-state resistance: 8 Bandwidth: 10 GHz Low off-state isolation: 20 dB at 5 GHz Low crosstalk: 36 dB at 5 GHz Differential input voltage V : 1.2 V (maximum) ID Differential AUX channel Low insertion loss: 1.1 dB at 5 MHz 1.8 dB at 360 MHz Low return loss: 18 dB at 5 MHz 16 dB at 360 MHzCBTL05024 NXP Semiconductors High performance MUX/deMUX switch for Thunderbolt applications Low ON-state resistance: 13 (typical) 16 (maximum) Bandwidth: 3 GHz Low off-state isolation: 80 dB at 5 MHz 55 dB at 360 MHz Low crosstalk: 26 dB at 2.7 GHz Common-mode input voltage V : 0 V to 3.3 V IC Differential input voltage V : 1.4 V (maximum) ID DDC channel ON-state resistor: 50 (maximum) 100 kHz 3.3 V voltage swing signal Both AUXIO+ and AUXIO outputs have 85 k ( 20 %) resistors The 85 k AUXIO pull-up resistor The 85 k AUXIO+ pull-down resistor is always present 2.2 DP MUX 2 : 1 switch Multiplexes between differential DP ML signal and LSTX/LSRX signals The DP ML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s The low speed DC-coupled signals LSTX and LSRX are 3.3 V single-ended signals that operate at 1 Mbit/s 5.4 Gbit/s DP-DPMLO path for DP MUX Low insertion loss for DP-DPMLO path: 1.2 dB at 2.7 GHz Low return loss for DP-DPMLO path: 15 dB at 2.7 GHz Low ON-state resistance for DP-DPMLO path: 9 High bandwidth: 5.5 GHz Low off-state isolation: 20 dB at 2.7 GHz Low crosstalk: 25 dB at 2.7 GHz Common-mode input voltage V : 0 V to 3.3 V IC Differential input voltage V : 1.4 V (maximum) ID LS-DPMLO path for DP MUX Low insertion loss: single-ended insertion loss (ON) is 1.0 dB at 5 MHz Low return loss: single-ended return loss (ON) is 20 dB at 5 MHz Low ON-state resistance: 16 (typical) for V =3.3 V DD High bandwidth: Single-ended 3 dB bandwidth is 1 GHz Low off-state isolation: single-ended insertion loss (OFF) is 60 dB at 5 MHz Low crosstalk: 40 dB at 5 GHz 2.3 General The input of the HPD (Hot Plug Detect) buffer is 5 V tolerant HPDOUT and CA DETOUT buffers CA DET input leakage current < 0.1 A to prevent driving the 1 M pull-down to a HIGH level Integrated LSRX buffer with 1 M pull-down resistor (R1) on the LSRX buffer input Integrated 8.75 k pull-up resistor (R4) on the LSTX pin CBTL05024 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4 27 March 2014 2 of 21