CBTL06DP212EE,118 NXP

CBTL06DP212 High-performance DisplayPort Gen2 2 : 1 multiplexer Rev. 2 3 November 2011 Product data sheet 1. General description CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. A typical application of CBTL06DP212 is on motherboards where one of two GPU DisplayPort sources needs to be selected to connect to a DisplayPort sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the bidirectional nature of the signal paths, CBTL06DP212 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. 2. Features and benefits 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort main link signals 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals 1 channel with 2 : 1 multiplexing/switching for HPD signal High-bandwidth: 5 GHz at 3dB Low insertion loss: 0.5 dB at 100 MHz 3dB at 5 GHz Low crosstalk: 35 dB at 3 GHz Low off-state isolation: 30 dB at 3 GHz Low return loss: 8dB at 3 GHz Very low intra-pair skew (5 ps typical) Very low inter-pair skew (< 80 ps) Switch/multiplexer position select CMOS input DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor Supports HDMI/DVI incorrect dongle connection Single 3.3 V power supply Operation current of 2 mA typicalCBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer ESD 8 kV HBM, 1 kV CDM ESD 2 kV HBM, 500 V CDM for control pins Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA48 package 3. Applications Motherboard applications requiring DisplayPort and PCI Express switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board connectors 4. Ordering information Table 1. Ordering information Type number Solder process Package Name Description Version CBTL06DP212EE Pb-free (SnAgCu TFBGA48 plastic thin fine-pitch ball grid array package SOT918-1 1 solder compound) 48 balls body 5 5 0.8 mm 1 Total height including solder balls after printed circuit board mounting = 1.15 mm maximum. 5. Marking Table 2. Package marking Line Marking Description 1 basic type number A6D212 B xxxxxxx diffusion lot number C ZPGyyww manufacturing code: Z = diffusion site P = assembly site G = lead-free yy = year code ww = week code 1 Industrial temperature range. CBTL06DP212 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 3 November 2011 2 of 18