GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Rev. 01 11 May 2004 Product data 1. Description The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 ) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation. The device is congured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. D-type ip-ops and D-type latches enable three modes of data transfer Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and congurable edge control provides the higher speed operation of GTL/GTL+ backplanes. The GTL1655 can be used at GTL (V = 1.2 V, V = 0.8 V) or GTL+ (V = 1.5 V, TT REF TT V = 1.0 V) signalling levels. Port A and the control inputs are compliant with REF LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with V providing the reference voltage input. REF The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data ow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data ow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins. To optimize signal integrity, the GTL1655 features an adjustable edge rate control (V ). By adjusting V between GND and V , a designer can adjust the Port B ERC ERC CC edge rate to suit an applications load conditions. The GTL1655 permits true live insertion capability by incorporating: BIAS V , to pre-charge outputs and avoid disturbing active data during card CC insertion. I to disable current ow through powered-off I/Os. off Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once V is above 1.5 V, the power-up CC 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to V via a pull-up resistor. CCGTL1655 Philips Semiconductors 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 2. Features Combination of D-type latches and D-type ip-ops for transceiver operation in clocked, latched or transparent mode Logic level translation between LVTTL and GTL/GTL+ signals HIGH-drive LOW-output-impedance (100 mA/12 ) on Port B Congurable rise and fall times on Port B Supports live insertion (I , Power-up 3-state, and BIAS V ) off CC Bus Hold on Port A inputs Over voltage tolerance on Port A Minimized switching noise through use of distributed V and GND pins CC Available in TSSOP64 package Industrial temperature range (- 40 Cto+85 C) ESD protection HBM EIA/JESD22-A114-A exceeds 2000 V CDM EIA/JESD22-C101 exceeds 1000 V Latch-up EIA/JEDS78 exceeds 200 mA 3. Quick reference data Table 1: Quick reference data GND = 0 V T =25 C t =t 2.5 ns amb r f Symbol Parameter Conditions Min Typ Max Unit t propagation delay, nAn to nBn V = 3.3 V V = GND - 3.9 - ns PLH CC ERC = 1.5 V V =1V V TT REF = 3.3 V V = GND - 4.4 - ns V CC ERC V = 1.5 V V =1V TT REF propagation delay, nBn to nAn V = 3.3 V - 2.6 - ns CC t propagation delay, nAn to nBn V = 3.3 V V = GND - 3.1 - ns PHL CC ERC = 1.5 V V =1V V TT REF V = 3.3 V V = GND - 2.7 - ns CC ERC V = 1.5 V V =1V TT REF propagation delay, nBn to nAn V = 3.3 V - 4.2 - ns CC C input capacitance (control pins) V =V or GND - 3 - pF i i CC C I/O capacitance, Port A V =V or GND - 7 - pF I/O i CC I/O capacitance, Port B V =V or GND - 8 - pF i CC 9397 750 12936 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 11 May 2004 2 of 23