GTL2008 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs Rev. 04 19 February 2010 Product data sheet 1. General description The GTL2008 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Functionally and footprint identical to the GTL2007, the GTL2008 LVTTL and GTL outputs were changed to put them into a high-impedance state when EN1 and EN2 are LOW, with the exception of 11BO because its normal state is LOW, so it is forced LOW. EN1 and EN2 will remain LOW until V is at normal voltage, the other inputs are in valid states CC and VREF is at its proper voltage to assure that the outputs will remain high-impedance through power-up. The GTL2008 has the enable function that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. This enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. This unexpected power-down could be from a power supply overload, a CPU thermal trip, or some other event of which the monitoring agent is unaware. A typical implementation would be to connect each enable line to the system power good signal or the individual enables to the VRD power good for each processor. Typically Xeon processors specify a V of 1.1 V to 1.2 V, as well as a nominal V of TT ref 0.73 V to 0.76 V. To allow for future voltage level changes that may extend V to 0.63 of ref V (minimum of 0.693 V with V of 1.1 V) the GTL2008 allows a minimum V of 0.66 V. TT TT ref Characterization results show that there is little DC or AC performance variation between these V levels. ref 2. Features and benefits Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver Operates at GTL/GTL/GTL+ signal levels EN1 and EN2 disable error output All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are LOW 3.0 V to 3.6 V operation LVTTL I/O not 5 V tolerant Series termination on the LVTTL outputs of 30 ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101GTL2008 NXP Semiconductors GTL translator with power good control and high-impedance outputs Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA Package offered: TSSOP28 3. Quick reference data Table 1. Quick reference data T =25 C amb Symbol Parameter Conditions Min Typ Max Unit C input/output capacitance A port V = 3.0 V or 0 V - 2.5 3.5 pF io O B port V =V or 0 V - 1.5 2.5 pF O TT V =0.73V V =1.1 V ref TT t LOW to HIGH nA to nBI see Figure 4 14 8 ns PLH propagation delay nBI to nA or nAO (open-drain outputs) 213 18 ns see Figure 14 t HIGH to LOW nA to nBI see Figure 4 2 5.5 10 ns PHL propagation delay nBI to nA or nAO (open-drain outputs) 2 4 10 ns see Figure 14 V =0.76V V =1.2 V ref TT t LOW to HIGH nA to nBI see Figure 4 14 8 ns PLH propagation delay nBI to nA or nAO (open-drain outputs) 213 18 ns see Figure 14 t HIGH to LOW nA to nBI see Figure 4 2 5.5 10 ns PHL propagation delay nBI to nA or nAO (open-drain outputs) 2 4 10 ns see Figure 14 4. Ordering information Table 2. Ordering information T = 40 Cto +85 C amb Type Topside Package number mark Name Description Version GTL2008PW GTL2008 TSSOP28 plastic thin shrink small outline package 28 leads body width 4.4 mm SOT361-1 GTL2008 4 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 19 February 2010 2 of 22