MC9S08FL8CLC NXP

Freescale Semiconductor Document NumberDocument Number: MC9S08FL16: MC9S08FL16 ReRevv.. 4, 5/2015 4, 5/2015 Data Sheet: Technical Data MC9S08FL16 MC9S08FL16 Series Covers: MC9S08FL16 and MC9S08FL8 32-Pin SDIP 32-Pin LQFP 1376-02 873A-03 Illegal address detection with reset Features: Flash block protection 8-Bit S08 Central Processor Unit (CPU) Development Support Up to 20 MHz CPU at 4.5 V to 5.5 V across Single-wire background debug interface temperature range of 40 C to 85 C Breakpoint capability to allow single breakpoint HC08 instruction set with added BGND instruction setting during in-circuit debugging (plus two more Support for up to 32 interrupt/reset sources breakpoints). On-chip in-circuit emulator (ICE) debug module On-Chip Memory containing two comparators and nine trigger Up to 16 KB flash read/program/erase over full modes. operating voltage and temperature Peripherals Up to 1024-byte random-access memory (RAM) Security circuitry to prevent unauthorized access IPC Interrupt priority controller to provide to RAM and flash contents hardware based nested interrupt mechanism ADC 12-channel, 8-bit resolution 2.5 s Power-Saving Modes conversion time automatic compare function Two low power stop modes reduced power wait 1.7 mV/C temperature sensor internal bandgap mode reference channel operation in stop optional Allows clocks to remain enabled to specific hardware trigger fully functional from 4.5 V to peripherals in stop3 mode 5.5 V TPM One 4-channel and one 2-channel Clock Source Options timer/pulse-width modulators (TPM) modules Oscillator (XOSC) Loop-control Pierce selectable input capture, output compare, or oscillator crystal or ceramic resonator range of buffered edge- or center-aligned PWM on each 31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz channel Internal Clock Source (ICS) Internal clock MTIM16 One 16-bit modulo timer with optional source module containing a prescaler frequency-locked-loop (FLL) controlled by internal SCI One serial communications interface or external reference precision trimming of module with optional 13-bit break LIN extensions internal reference allows 0.2% resolution and 2% deviation over temperature and voltage supports Input/Output bus frequencies up to 10 MHz 30 GPIOs including 1 output-only pin and 1 input-only pin System Protection Watchdog computer operating properly (COP) Package Options reset with option to run from dedicated 1 kHz 32-pin SDIP internal clock source or bus clock 32-pin LQFP Low-voltage detectionwith reset or interrupt selectable trip points Illegal opcode detection with reset This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2009-2015. All rights reserved.Table of Contents 1 MCU Block Diagram . 3 Characteristics . 19 2 System Clock Distribution . 4 5.9 AC Characteristics . 21 3 Pin Assignments 5 5.9.1 Control Timing . 22 4 Memory Map . 8 5.9.2 TPM Module Timing 23 5 Electrical Characteristics . 9 5.10 ADC Characteristics . 24 5.1 Introduction . 9 5.11 Flash Specifications 26 5.2 Parameter Classification . 9 5.12 EMC Performance . 27 5.3 Absolute Maximum Ratings . 9 5.12.1Radiated Emissions . 27 5.4 Thermal Characteristics . 10 6 Ordering Information . 27 5.5 ESD Protection and Latch-Up Immunity 11 7 Package Information . 28 5.6 DC Characteristics . 12 7.1 Mechanical Drawings . 28 5.7 Supply Current Characteristics . 17 5.8 External Oscillator (XOSC) and ICS Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: