MFRC631 High performance ISO/IEC 14443 A/B reader solution Rev. 3.3 4 February 2014 Product data sheet 227433 COMPANY PUBLIC 1. Introduction This document describes the functionality and electrical specifications of the contactless reader/writer IC MFRC631. 2. General description The MFRC631 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. The MFRC631 transceiver IC supports the following operating modes Read/write mode supporting ISO/IEC 14443A/MIFARE Read/write mode supporting ISO/IEC 14443B The MFRC631s internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional active circuitry. The digital module manages the complete ISO/IEC 14443A framing and error detection functionality (parity and CRC). The MFRC631 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight, MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The MFRC631 supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions. The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer communication scheme except anticollision. The anticollision needs to be implemented in the firmware of the host controller as well as in the upper layers. The following host interfaces are supported: Serial Peripheral Interface (SPI) Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply) 2 I C-bus interface (two versions are implemented: I2C and I2CL) The MFRC631 supports the connection of a secure access module (SAM). A dedicated separate I2C interface is implemented for a connection of the SAM. The SAM can be used for high secure key storage and acts as a very performant crypto coprocessor. A dedicated SAM is available for connection to the MFRC631. 3. Features and benefits High RF output power frontend IC for transfer speed up to 848 kbit/sMFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B Supports MIFARE Classic encryption in read/write mode Low-Power Card Detection Compliance to EMV contactless protocol specification V2.0.1 on RF level can be achieved Antenna connection with minimum number of external components Supported host interfaces: SPI up to 10 Mbit/s 2 I C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage supply 2 Separate I C-bus interface for connection of a secure access module (SAM) FIFO buffer with size of 512 byte for highest transaction performance Flexible and efficient power saving modes including hard power down, standby and low-power card detection Cost saving by integrated PLL to derive system CPU clock from 27.12 MHz RF quartz crystal 3 V to 5.5 V power supply Up to 8 free programmable input/output pins Typical operating distance in read/write mode for communication to a ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and tuning 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V supply voltage 3 5 5.5 V DD 1 V PVDD supply voltage 35 V V DD(PVDD) DD V TVDD supply voltage 3 5 5.5 V DD(TVDD) 2 I power-down current PDOWN pin pulled HIGH - 8 40 nA pd I supply current - 17 20 mA DD 3 4 I TVDD supply current - 100 200 mA DD(TVDD) T ambient temperature 25 +25 +85 C amb T storage temperature no supply voltage applied 40 +25 +100 C stg 1 VDD(PVDD) must always be the same or lower voltage than VDD. 2 I is the sum of all supply currents pd 3 I depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2. DD(TVDD) 4 Typical value: Assumes the usage of a complementary driver configuration and an antenna matched to 40 between pins TX1, TX2 at 13.56 MHz. MFRC631 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved. Product data sheet Rev. 3.3 4 February 2014 COMPANY PUBLIC 227433 2 of 120