PSMN5R9-30YL,115 NXP

PSMN5R9-30YL N-channel 6.1 m 30 V TrenchMOS logic level FET in LFPAK Rev. 2 16 May 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits High efficiency due to low switching Suitable for logic level gate drive and conduction losses sources 1.3 Applications Class-D amplifiers Motor control DC-to-DC converters Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C; T 175C --30 V DS j j I drain current T =25C; V =10V; --78 A D mb GS see Figure 1 P total power T = 25 C; see Figure 2 --63 W tot mb dissipation Static characteristics R drain-source V =10V; I =20 A; T =25C - 5.2 6.1 m DSon GS D j on-state resistance Dynamic characteristics Q gate-drain charge V =10V; I =60 A; V =15V; -4.8 -nC GD GS D DS see Figure 14; see Figure 15 Q total gate charge V =4.5 V; I =60A; V =15V; -10.5- nC G(tot) GS D DS see Figure 14; see Figure 15 Avalanche ruggedness E non-repetitive V =10V; T =25C; --28 mJ DS(AL)S GS j(init) drain-source I =78A; V 30 V; R =50 ; D sup GS avalanche energy unclamped LFPAKPSMN5R9-30YL NXP Semiconductors N-channel 6.1 m 30 V TrenchMOS logic level FET in LFPAK 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source mb D 2S source 3S source G 4 G gate mbb076 S mb D mounting base; connected to drain 1234 SOT669 (LFPAK; Power-SO8) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN5R9-30YL LFPAK; Power-SO8 plastic single-ended surface-mounted package; 4 leads SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage T 25 C; T 175 C - 30 V DS j j V peak drain-source voltage t 25 ns; f 500 kHz; E 90 J; pulsed - 35 V DSM p DS(AL) V drain-gate voltage T 25 C; T 175 C; R =20k -30 V DGR j j GS V gate-source voltage -20 20 V GS I drain current V =10V; T = 100 C; see Figure 1 -55 A D GS mb V =10V; T = 25 C; see Figure 1 -78 A GS mb I peak drain current pulsed; t 10 s; T = 25 C; see Figure 3 - 310 A DM p mb P total power dissipation T = 25 C; see Figure 2 -63 W tot mb T storage temperature -55 175 C stg T junction temperature -55 175 C j Source-drain diode I source current T =25C - 78 A S mb I peak source current pulsed; t 10 s; T = 25 C - 310 A SM p mb Avalanche ruggedness E non-repetitive drain-source V =10V; T =25 C; I =78A; -28 mJ DS(AL)S GS j(init) D avalanche energy V 30 V; R =50 ; unclamped sup GS PSMN5R9-30YL All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 16 May 2011 2 of 14