PTN3356R1 ROM-based low-power DisplayPort to VGA adapter Rev. 2.2 16 August 2016 Product data sheet 1. General description PTN3356R1 is a ROM-based DisplayPort to VGA adapter optimized primarily for motherboard applications, to convert a DisplayPort signal from the chip set to an analog video signal that directly connects to the VGA connector. PTN3356R1 integrates a DisplayPort receiver, a high-speed triple video digital-to-analog converter that supports a wide range of display resolutions, for example, VGA to WUXGA (see Table 8). PTN3356R1 supports two DisplayPort lanes operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. 2 PTN3356R1 supports I C-bus over AUX per DisplayPort standard (Ref. 1), and bridges the VESA DDC channel to the DisplayPort Interface. PTN3356R1 is powered from a 3.3 V power supply and consumes approximately 200 mW of power for video streaming in WUXGA resolution and 410 W of power in Low-power mode. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. PTN3356R1 also aids in monitor detection by performing load sensing on RGB lines and reporting sink connection status to the source. 2. Features and benefits 2.1 VESA-compliant DisplayPort converter Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane 9 BER (Bit Error Rate) better than 10 DisplayPort Link down-spreading supported 1 MHz AUX channel Supports native AUX CH syntax 2 Supports I C-bus over AUX CH syntax Active HIGH Hot Plug Detect (HPD) signal to the source 2.2 VESA-compliant eDP extensions Supports Alternate Scrambler Seed Reset (ASSR) Supports Alternate Enhanced Framing mode - Enhanced Framing 2.3 DDC channel output 2 I C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see Ref. 2)PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 2.4 Analog video output VSIS 1.2 compliance (Ref. 3) for supported video output modes Analog RGB current-source outputs 3.3 V VSYNC and HSYNC outputs Pixel clock up to 240 MHz Triple 8-bit Digital-to-Analog Converter (DAC) Direct drive of double terminated 75 load with standard 700 mV (peak-to-peak) signals 2.5 General features Monitor presence detection through load detection scheme. Connection/disconnection reported via HPD IRQ and DPCD update. 1 Wide set of display resolutions are supported : 1920 1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate 2048 1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate 2048 1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate UXGA: 1600 1200, 60 Hz, 162 MHz pixel clock rate SXGA: 1280 1024, 60 Hz, 108 MHz pixel clock rate XGA: 1024 768, 60 Hz, 65 MHz pixel clock rate SVGA: 800 600, 60 Hz, 40 MHz pixel clock rate VGA: 640 480, 60 Hz, 25 MHz pixel clock rate Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp 1 Bits per color (bpc) supported 6, 8 bits supported 10, 12, 16 bits supported by truncation to 8 MSBs All VGA colorimetry formats (RGB) supported Power modes (when the application design is as per Figure 4) Active-mode power consumption: ~200 mW at WUXGA, 1920 1200, 60 Hz (18 bpc) 410 W at Low-power mode Supports flexible choice of timing reference On-board oscillator with external crystal, ceramic resonator Different frequencies supported: 24 MHz, 25 MHz, 27 MHz ESD protection: 7 kV HBM Single power supply (3.3 V) for easy integration in the platforms Commercial temperature range: 0 C to 85 C 32-pin HVQFN, 5 mm 5mm 0.85 mm (nominal) 0.5 mm pitch lead-free package 1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link. PTN3356R1 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 2.2 16 August 2016 2 of 38