74AC373, 74ACT373 Octal Transparent Latch with 3-STATE Outputs January 2008 74AC373, 74ACT373 Octal Transparent Latch with 3-STATE Outputs Features General Description I and I reduced by 50% The AC/ACT373 consists of eight latches with 3-STATE CC OZ outputs for bus organized system applications. The flip- Eight latches in a single package flops appear transparent to the data when Latch Enable 3-STATE outputs for bus interfacing (LE) is HIGH. When LE is LOW, the data that meets the Outputs source/sink 24mA setup time is latched. Data appears on the bus when the ACT373 has TTL-compatible inputs Output Enable (OE ) is LOW. When OE is HIGH, the bus output is in the high impedance state. Ordering Information Package Order Number Number Package Description 74AC373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC373, 74ACT373 Rev. 1.5.074AC373, 74ACT373 Octal Transparent Latch with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names Description D D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O O 3-STATE Latch Outputs 0 7 Functional Description Truth Table The AC/ACT373 contains eight D-type latches with Inputs Outputs 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. LE OE D O n n n In this condition the latches are transparent, i.e., a latch XHX Z output will change state each time its D-type input HL L L changes. When LE is LOW, the latches store the infor- mation that was present on the D-type inputs a setup HLH H time preceding the HIGH-to-LOW transition of LE. The LL X O 0 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard H = HIGH Voltage Level outputs are in the 2-state mode. When OE is HIGH, the L = LOW Voltage Level standard outputs are in the high impedance mode but Z = High Impedance this does not interfere with entering new data into the X = Immaterial latches. O = Previous O before HIGH-to-LOW transition 0 0 of Latch Enable 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC373, 74ACT373 Rev. 1.5.0 2