74AC573, 74ACT573 Octal Latch with 3-STATE Outputs January 2008 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Features General Description I and I reduced by 50% The 74AC573 and 74ACT573 are high-speed octal CC OZ latches with buffered common Latch Enable (LE) and Inputs and outputs on opposite sides of package buffered common Output Enable (OE) inputs. allowing easy interface with microprocessors Useful as input or output port for microprocessors The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and Functionally identical to 74AC373 and 74ACT373 outputs on opposite sides. 3-STATE outputs for bus interfacing Outputs source/sink 24mA 74ACT573 has TTL-compatible inputs Ordering Information Package Order Number Number Package Description 74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC573, 74ACT573 Rev. 1.6.074AC573, 74ACT573 Octal Latch with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names Description D D Data Inputs 0 7 LE Latch Enable Input OE 3-STATE Output Enable Input O O 3-STATE Latch Outputs 0 7 Functional Description Truth Table The 74AC573 and 74ACT573 contain eight D-type Inputs Outputs latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters n OE LE D O n the latches. In this condition the latches are transparent, LH H H i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the LH L L information that was present on the D-type inputs a LL X O 0 setup time preceding the HIGH-to-LOW transition of LE. HX X Z The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are H = HIGH Voltage enabled. When OE is HIGH the buffers are in the high L = LOW Voltage impedance mode but this does not interfere with entering Z = High Impedance new data into the latches. X = Immaterial O = Previous O before HIGH-to-LOW transition of 0 0 Latch Enable 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC573, 74ACT573 Rev. 1.6.0 2