74F139SC ON Semiconductor

74F139 Dual 1-of-4 Decoder/Demultiplexer April 1988 Revised September 2000 74F139 Dual 1-of-4 Decoder/Demultiplexer General Description Features The F139 is a high-speed, dual 1-of-4 decoder/demulti- Multifunction capability plexer. The device has two independent decoders, each Two completely independent 1-of-4 decoders accepting two inputs and providing four mutually exclusive Active LOW mutually exclusive outputs active LOW outputs. Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. Each half of the F139 can be used as a function generator providing all four minterms of two variables. Ordering Code: Order Number Package Number Package Description 74F139SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F139PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Connection Diagram Truth Table Inputs Outputs IEEE/IEC E A A O O O O 0 1 0 1 2 3 H X X HHHH L LLL H H H L H LH LH H L L HHH L H L HHHHH L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 2000 Fairchild Semiconductor Corporation DS009479 www.fairchildsemi.comUnit Loading/Fan Out U.L. Input I /I IH IL Pin Names Description Output I /I HIGH/LOW OH OL A , A Address Inputs 1.0/1.0 20 A/0.6 mA 0 1 E Enable Inputs (Active LOW) 1.0/1.0 20 A/0.6 mA O O Outputs (Active LOW) 50/33.3 1 mA/20 mA 0 3 Functional Description The F139 is a high-speed dual 1-of-4 decoder/demulti- plexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A A ) and pro- 0 1 vides four mutually exclusive active LOW Outputs (O O ). 0 3 Each decoder has an active LOW enable (E). When E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4-output demultiplexer application. Each half of the F139 generates all four minterms of two variables. These four minterms are useful in some applica- tions, replacing multiple gate functions as shown in Figure 1, and thereby reducing the number of packages required in a logic network. FIGURE 1. Gate Functions (each half) Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F139