74F153 Dual 4-Input Multiplexer
April 1988
Revised September 2000
74F153
Dual 4-Input Multiplexer
General Description
The F153 is a high-speed dual 4-input multiplexer with
common select inputs and individual enable inputs for each
section. It can select two lines of data from four sources.
The two buffered outputs present data in the true
(non-inverted) form. In addition to multiplexer operation,
the F153 can generate any two functions of three variables.
Ordering Code:
Order Number Package Number Package Description
74F153SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F153SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F153PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Logic Symbols Connection Diagram
IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009482 www.fairchildsemi.comUnit Loading/Fan Out
U.L. Input I /I
IH IL
Pin Names Description
Output I /I
HIGH/LOW
OH OL
I I Side A Data Inputs 1.0/1.0 20 A/0.6 mA
0a 3a
I I Side B Data Inputs 1.0/1.0 20 A/0.6 mA
0b 3b
S , S Common Select Inputs 1.0/1.0 20 A/0.6 mA
0 1
E Side A Enable Input (Active LOW) 1.0/1.0 20 A/0.6 mA
a
E Side B Enable Input (Active LOW) 1.0/1.0 20 A/0.6 mA
b
Z Side A Output 50/33.3 1 mA/20 mA
a
Z Side B Output 50/33.3 1 mA/20 mA
b
Truth Table Functional Description
The F153 is a dual 4-input multiplexer. It can select two bits
Select Inputs Inputs (a or b) Output
of data from up to four sources under the control of the
common Select inputs (S , S ). The two 4-input multiplexer
0 1
S S I I I I
E Z
0 1 0 1 2 3
circuits have individual active LOW Enables (E , E ) which
a b
X X H XXXX L
can be used to strobe the outputs independently. When the
Enables (E , E ) are HIGH, the corresponding outputs (Z ,
a b a
L L L L XXX L
Z ) are forced LOW. The F153 is the logic implementation
b
L L L H XXX H
of a 2-pole, 4-position switch, where the position of the
switch is determined by the logic levels supplied to the two
H L LX LX X L
Select inputs. The logic equations for the outputs are as
HL L X H X X H
follows:
LH L X X L X L Z = E (I S S + I S S +
a a 0a 1 0 1a 1 0
I S S + I S S )
2a 1 0 3a 1 0
LH L X X H X H
Z = E (I S S + I S S +
b b 0b 1 0 1b 1 0
H H L XXX L L
I S S + I S S )
2b 1 0 3b 1 0
H H L XXX H H
The F153 can be used to move data from a group of regis-
H = HIGH Voltage Level
ters to a common output bus. The particular register from
L = LOW
which the data came would be determined by the state of
X = Immaterial
the Select inputs. A less obvious application is as a func-
tion generator. The F153 can generate two functions of
three variables. This is useful for implementing highly irreg-
ular random logic.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F153