74F161A, 74F163A Synchronous Presettable Binary Counter
April 2007
74F161A, 74F163A
tm
Synchronous Presettable Binary Counter
Features General Description
Synchronous counting and loading The 74F161A and 74F163A are high-speed synchro-
nous modulo-16 binary counters. They are synchro-
High-speed synchronous expansion
nously presettable for application in programmable
Typical count frequency of 120MHz
dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming
synchronous multi-stage counters. The 74F161A has an
asynchronous Master-Reset input that overrides all other
inputs and forces the outputs LOW. The 74F163A has a
Synchronous Reset input that overrides counting and
parallel loading and allows the outputs to be simulta-
neously reset on the rising edge of the clock. The
74F161A and 74F163A are high-speed versions of the
74F161 and 74F163.
Ordering Information
Order Package
Number Number Package Description
74F161ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74F161ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74F163ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74F163ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
Connection Diagrams
74F161A 74F163A
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F161A, 74F163A Rev. 1.0.274F161A, 74F163A Synchronous Presettable Binary Counter
Logic Symbols
74F161A 74F163A
IEEE/IEC IEEE/IEC
74F161A 74F163A
Unit Loading/Fan Out
U.L. Input I / I
IH IL
Pin Names Description HIGH / LOW Output I / I
OH OL
CEP Count Enable Parallel Input 1.0 / 1.0 20A / -0.6mA
CET Count Enable Trickle Input 1.0 / 2.0 20A / -1.2mA
CP Clock Pulse Input (Active Rising Edge) 1.0 / 1.0 20A / -0.6 mA
MR (74F161A) Asynchronous Master Reset Input (Active LOW) 1.0 / 1.0 20A / -0.6 mA
SR (74F163A) Synchronous Reset Input (Active LOW) 1.0 / 2.0 20A / -1.2 mA
P P Parallel Data Inputs 1.0 / 1.0 20A / -0.6 mA
0 3
PE Parallel Enable Input (Active LOW) 1.0 / 2.0 20A / -1.2mA
Q Q Flip-Flop Outputs 50 / 33.3 -1mA / 20mA
0 3
TC Terminal Count Output 50 / 33.3 -1mA / 20mA
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F161A, 74F163A Rev. 1.0.2 2