74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs October 2000 Revised June 2005 74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs General Description Features The LVTH162373 contains sixteen non-inverting latches Input and output interface capability to systems at with 3-STATE outputs and is intended for bus oriented 5V V CC applications. The device is byte controlled. The flip-flops Bushold data inputs eliminate the need for external appear transparent to the data when the Latch Enable (LE) pull-up resistors to hold unused inputs is HIGH. When LE is LOW, the data that meets the setup Live insertion/extraction permitted time is latched. Data appears on the bus when the Output Power Up/Down high impedance provides glitch-free Enable (OE) is LOW. When OE is HIGH, the outputs are in bus loading a high impedance state. Outputs include equivalent series resistance of 25: to The LVTH162373 is designed with equivalent 25 : series make external termination resistors unnecessary and resistance in both the HIGH and LOW states of the output. reduce overshoot and undershoot This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceiv- Functionally compatible with the 74 series 16373 ers/transmitters. Latch-up performance exceeds 500 mA The LVTH162373 data inputs include bushold, eliminating ESD performance: the need for external pull-up resistors to hold unused Human-body model 2000V inputs. Machine model 200V These latches are designed for low-voltage (3.3V) V CC Charged-device model 1000V applications, but with the capability to provide a TTL inter- face to a 5V environment. The LVTH162373 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Ordering Code: Package Order Number Package Description Number 74LVTH162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide TUBES 74LVTH162373MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide (Note 1) TAPE and REEL 74LVTH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide TUBES 74LVTH162373MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 1) TAPE and REEL Note 1: Use this Order Number to receive devices in Tape and Reel. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500354 www.fairchildsemi.comConnection Diagram Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n LE Latch Enable Input n I I Inputs 0 15 O O 3-STATE Outputs 0 15 Truth Tables Inputs Outputs LE OE I I O O 1 1 0 7 0 7 X H X Z H L L L H L H H L L X O o Inputs Outputs LE OE I I O O 2 2 8 15 8 15 X H X Z H L L L H L H H L L X O o H HIGH Voltage Level L LOW Voltage Level X Immaterial Z HIGH Impedance O Previous output prior to HIGH-to-LOW transition of LE o Functional Description The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE ) input is HIGH, data on the D enters the n n latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LE is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW n transition of LE . The 3-STATE standard outputs are controlled by the Output Enable (OE ) input. When OE is LOW, the n n n standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but n this does not interfere with entering new data into the latches. www.fairchildsemi.com 2 74LVTH162373