74LVT16373 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
January 1999
Revised June 2005
74LVT16373 74LVTH16373
Low Voltage 16-Bit Transparent Latch
with 3-STATE Outputs
General Description Features
The LVT16373 and LVTH16373 contain sixteen non-invert- Input and output interface capability to systems at
ing latches with 3-STATE outputs and is intended for bus 5V V
CC
oriented applications. The device is byte controlled. The
Bushold data inputs eliminate the need for external
flip-flops appear transparent to the data when the Latch
pull-up resistors to hold unused inputs (74LVTH16373),
Enable (LE) is HIGH. When LE is LOW, the data that meets
also available without bushold feature (74LVT16373)
the setup time is latched. Data appears on the bus when
Live insertion/extraction permitted
the Output Enable (OE) is LOW. When OE is HIGH, the
Power Up/Power Down high impedance provides
outputs are in a high impedance state.
glitch-free bus loading
The LVTH16373 data inputs include bushold, eliminating
Outputs source/sink 32 mA/ 64 mA
the need for external pull-up resistors to hold unused
inputs. Functionally compatible with the 74 series 16373
These latches are designed for low-voltage (3.3V) V
Latch-up performance exceeds 500 mA
CC
applications, but with the capability to provide a TTL inter-
ESD performance:
face to a 5V environment. The LVT16373 and LVTH16373
Human-body model ! 2000V
are fabricated with an advanced BiCMOS technology to
Machine model ! 200V
achieve high speed operation similar to 5V ABT while
Charged-device model ! 1000V
maintaining a low power dissipation.
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number Package Description
74LVT16373GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Note 1) (Preliminary) [TAPE and REEL]
74LVT16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
(Note 2)
74LVT16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
(Note 2)
74LVTH16373GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Note 1) (Preliminary) [TAPE and REEL]
74LVTH16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
(Note 2)
74LVTH16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
(Note 2)
Note 1: BGA package available in Tape and Reel only.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code.
Logic Symbol
2005 Fairchild Semiconductor Corporation DS012021 www.fairchildsemi.comConnection Diagrams Pin Descriptions
Pin Assignment for SSOP and TSSOP Pin Names Description
OE Output Enable Input (Active LOW)
n
LE Latch Enable Input
n
I I Inputs
0 15
O O 3-STATE Outputs
0 15
NC No Connect
FBGA Pin Assignments
1 234 56
A O NC OE LE NC I
0 1 1 0
B O O NC NC I I
2 1 1 2
C O O V V I I
4 3 CC CC 3 4
D O O GND GND I I
6 5 5 6
E O O GND GND I I
8 7 7 8
F O O GND GND I I
10 9 9 10
G O O V V I I
12 11 CC CC 11 12
H O O NC NC I I
14 13 13 14
J O NC OE LE NC I
15 2 2 15
Truth Tables
Inputs Outputs
LE OE I I O O
1 1 0 7 0 7
Pin Assignment for FBGA
X H X Z
H L L L
H L H H
L L X O
o
Inputs Outputs
LE OE I I O O
2 2 8 15 8 15
X H X Z
H L L L
H L H H
L L X O
o
(Top Thru View)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z HIGH Impedance
O Previous output prior to HIGH-to-LOW transition of LE
o
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74LVT16373 74LVTH16373