CAV24C256 2 EEPROM Serial 256-Kb I C - Automotive Grade 1 Description 2 The CAV24C256 is a EEPROM Serial 256Kb I C, internally organized as 32,768 words of 8 bits each. www.onsemi.com It features a 64byte page write buffer and supports the Standard 2 (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). External address pins make it possible to address up to eight TSSOP8 CAV24C256 devices on the same bus. Y SUFFIX OnChip ECC (Error Correction Code) makes the device suitable CASE 948AL for high reliability applications. Features Automotive AECQ100 Grade 1 (40C to +125C) Qualified SOIC8 2 W SUFFIX Supports Standard, Fast and FastPlus I C Protocol CASE 751BD 2.5 V to 5.5 V Supply Voltage Range 64Byte Page Write Buffer Hardware Write Protection for Entire Memory PIN CONFIGURATION 2 Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs 1 A V 0 CC (SCL and SDA) A WP 1 Low Power CMOS Technology SCL A 2 1,000,000 Program/Erase Cycles V SDA SS 100 Year Data Retention 8lead SOIC and TSSOP Packages SOIC (W), TSSOP (Y) This Device is PbFree, Halogen Free/BFR Free, and RoHS For the location of Pin 1, please consult the corresponding package drawing. Compliant V CC PIN FUNCTION Pin Name Function SCL A , A , A Device Address 0 1 2 SDA Serial Data CAV24C256 SDA A , A , A 2 1 0 SCL Serial Clock WP Write Protect WP V Power Supply CC V Ground SS V SS Figure 1. Functional Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: April, 2019 Rev. 2 CAV24C256/DCAV24C256 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Notes 3, 4) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C. CC 4. This device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz/1 MHz 1 mA CCR SCL I Write Current 3 mA CCW I Standby Current All I/O Pins at GND or V T = 40C to +125C 5 A SB CC A I I/O Pin Leakage Pin at GND or V T = 40C to +125C 2 A L CC A V Input Low Voltage 0.5 0.3 V V IL CC V Input High Voltage 0.7 V V + 0.5 V IH CC CC V Output Low Voltage I = 3.0 mA 0.4 V OL OL Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specied.) CC A Symbol Parameter Conditions Max Units C (Note 5) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 5) Input Capacitance (other pins) V = 0 V 6 pF IN IN I , I (Note 6) WP Input Current, Address Input V < V , V = 5.5 V 75 A WP A IN IH CC Current (A , A , A ) 0 1 2 V < V , V = 3.3 V 50 IN IH CC V > V 2 IN IH 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 6. When not driven, the WP, A , A , A pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively 0 1 2 strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC www.onsemi.com 2