CAV25128 EEPROM Serial 128-Kb SPI Automotive Grade 1 Description The CAV25128 is a EEPROM Serial 128Kb SPI Automotive Grade 1 device internally organized as 16Kx8 bits. This features a www.onsemi.com 64byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25128 device. The SOIC8 device features software and hardware write protection, including V SUFFIX partial as well as full array protection. CASE 751BD OnChip ECC (Error Correction Code) makes the device suitable for high reliability applications. Features Automotive AECQ100 Grade 1 (40C to +125C) Qualified TSSOP8 Y SUFFIX 10 MHz SPI Compatible CASE 948AL 2.5 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 64byte Page Write Buffer PIN CONFIGURATION Additional Identification Page with Permanent Write Protection 1 V CS CC Selftimed Write Cycle SO HOLD WP SCK Hardware and Software Protection V SI SS Block Write Protection Protect 1/4, 1/2 or Entire EEPROM Array SOIC (V), TSSOP (Y) Low Power CMOS Technology 1,000,000 Program/Erase Cycles PIN FUNCTION 100 Year Data Retention Pin Name Function 8Lead SOIC and TSSOP Packages CS Chip Select This Device is PbFree, Halogen Free/BFR Free, and RoHS SO Serial Data Output Compliant WP Write Protect V CC V Ground SS SI Serial Data Input SI SCK Serial Clock CS CAV25128 SO HOLD Hold Transmission Input WP V Power Supply HOLD CC SCK ORDERING INFORMATION V SS See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Figure 1. Functional Symbol Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: April, 2019 Rev. 2 CAV25128/DCAV25128 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature 45 to +130 C Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C. CC 4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A Symbol Parameter Test Conditions Min Max Units I Supply Current (Read Mode) Read, SO open, f = 10 MHz 2 mA CCR SCK I Supply Current (Write Mode) Write, CS = V 2 mA CCW CC I Standby Current V = GND or V , CS = V , 3 A SB1 IN CC CC WP = V , V = 5.5 V CC CC I Standby Current V = GND or V , CS = V , 5 A SB2 IN CC CC WP = GND, V = 5.5 V CC I Input Leakage Current V = GND or V 2 2 A L IN CC I Output Leakage Current CS = V V = GND or V 2 2 A LO CC OUT CC V Input Low Voltage 0.5 0.3 V V IL CC V Input High Voltage 0.7 V V + 0.5 V IH CC CC V Output Low Voltage I = 3.0 mA 0.4 V OL OL V Output High Voltage I = 1.6 mA V 0.8 V V OH OH CC Table 4. PIN CAPACITANCE (Note 5) (T = 25C, f = 1.0 MHz, V = +5.0 V) A CC Symbol Test Conditions Min Typ Max Units C Output Capacitance (SO) V = 0 V 8 pF OUT OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) V = 0 V 8 pF IN IN 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. www.onsemi.com 2