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Advancements in both silicon and Max r = 11.0m : at V = 4.5V, I = 11.5A DS(on) GS D package technologies have been combined to offer the lowest Advanced Package and Silicon combination for r while maintaining excellent switching performance. DS(on) low r and high efficiency DS(on) Applications MSL1 robust package design Low Side for Synchronous Buck to Power Core Processor RoHS Compliant Secondary Side Synchronous Rectifier Low Side Switch in POL DC/DC Converter Oring FET/ Load Switch Bottom Top Pin 1 S D 5 4 G S S G D 6 3 S D 7 2 S D D D 8 1 S D D Power 56 MOSFET Maximum Ratings T = 25C unless otherwise noted A Symbol Parameter Ratings Units V Drain to Source Voltage 30 V DS V Gate to Source Voltage 20 V GS Drain Current -Continuous (Package limited) T = 25C 35 C -Continuous (Silicon limited) T = 25C 63 C I A D -Continuous T = 25C (Note 1a) 14 A -Pulsed 100 E Single Pulse Avalanche Energy (Note 3) 216 mJ AS Power Dissipation T = 25C 50 C P W D Power Dissipation T = 25C (Note 1a) 2.5 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 2.5 T JC C/W R Thermal Resistance, Junction to Ambient (Note 1a) 50 T JA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS8680 FDMS8680 Power 56 13 12mm 3000units 1 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMS8680 Rev.C3 :