MC10ELT25, MC100ELT25
-5 VDifferential ECL to TTL
Translator
Description
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used, a +5 V, 5.2 V (or 4.5 V) and ground
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are required. The small outline 8-lead package and the single gate of
the ELT25 makes it ideal for those applications where space,
MARKING DIAGRAMS*
performance and low power are at a premium.
The V pin, an internally generated voltage supply, is available to
BB 8 8
8
this device only. For single-ended input conditions, the unused
HLT25 KLT25
1
differential input is connected to V as a switching reference voltage.
ALYW ALYW
BB
V may also rebias AC coupled inputs. When used, decouple V
BB BB
SOIC8
1 1
and V via a 0.01 F capacitor and limit current sourcing or sinking
CC
D SUFFIX
to 0.5 mA. When not used, V should be left open.
BB CASE 751
The 100 Series contains temperature compensation.
Features
8 8
8
2.6 ns Typical Propagation Delay
1
HT25 KT25
ALYW ALYW
100 MHz F CLK
MAX
TSSOP8
24 mA TTL Outputs
DT SUFFIX 1 1
CASE 948R
Flow Through Pinouts
Operating Range: V = 4.5 V to 5.5 V with GND = 0 V;
CC
V = 4.2 V to 5.7 V with GND = 0 V
EE
Internal Input 50 K Pulldown Resistors
Q Output will default HIGH with inputs open or < 1.3 V
14
14
These Devices are PbFree, Halogen Free/BFR Free and are RoHS DFN8
MN SUFFIX
Compliant
CASE 506AA
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5F = MC10 Y = Year
2U = MC100 W = Work Week
M = Date Code = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
August, 2015 Rev. 14 MC10ELT25/D
5F M
2U M
MC10ELT25, MC100ELT25
Table 1. PIN DESCRIPTION
V 1 8 V
EE CC
Pin Function
TTL D, D ECL Differential Inputs
D 2 7 Q
Q TTL Output
ECL
V Reference Voltage Output
BB
D 3 6 NC
V Positive Supply
CC
V Negative Supply
EE
V GND
BB45
GND Ground
NC No Connect
Figure 1. 8Lead Pinout (Top View) and Logic
EP (DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
Diagram
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model > 1 kV
Machine Model > 400 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg
SOIC8 Level 1
TSSOP8 Level 3
DFN8 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 38 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V Positive Power Supply GND = 0 V V = 5.0 V 7 V
CC EE
V Negative Power Supply GND = 0 V V = +5.0 V 8 V
EE CC
V Input Voltage GND = 0 V 0 to V V
IN EE
I V Sink/Source 0.5 mA
BB BB
T Operating Temperature Range 40 to +85 C
A
T Storage Temperature Range 65 to +150 C
stg
Thermal Resistance (JunctiontoAmbient) 0 lfpm SOIC8 190 C/W
JA
500 lfpm SOIC8 130 C/W
Thermal Resistance (JunctiontoCase) Standard Board SOIC8 41 to 44 C/W
JC
Thermal Resistance (JunctiontoAmbient) 0 lfpm TSSOP8 185 C/W
JA
500 lfpm TSSOP8 140 C/W
Thermal Resistance (JunctiontoCase) Standard Board TSSOP8 41 to 44 5% C/W
JC
Thermal Resistance (JunctiontoAmbient) 0 lfpm DFN8 129 C/W
JA
500 lfpm DFN8 84 C/W
T Wave Solder PbFree <2 to 3 sec @ 260C 265 C
sol
Thermal Resistance (JunctiontoCase) (Note 2) DFN8 35 to 40 C/W
JC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
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2