3.3 VECL 2Input Differential AND/NAND MC100LVEL05 Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and www.onsemi.com operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC 8 8 performance at low voltage power supplies. 1 1 Because a negative 2-input NAND is equivalent to a 2-input OR SOIC8 TSSOP8 function, the differential inputs and outputs of the device allows the D SUFFIX DT SUFFIX LVEL05 to also be used as a 2-input differential OR/NOR gate. CASE 751 CASE 948R Features 340 ps Propagation Delay MARKING DIAGRAMS* High Bandwidth Output Transitions 8 ESD Protection: 8 > 4 kV Human Body Mode KVL05 KV05 ALYW ALYW > 200 V Machine Model The 100 Series Contains Temperature Compensation 1 1 PECL Mode Operating Range: V = 3.0 V to 3.8 V CC SOIC8 TSSOP8 with V = 0 V EE A = Assembly Location NECL Mode Operating Range: V = 0 V CC L = Wafer Lot with V = 3.0 V to 3.8 V EE Y = Year Internal Input Pulldown Resistors W = Work Week M = Date Code Q Output will Default LOW with All Inputs Open or at V EE = Pb-Free Package Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test (Note: Microdot may be in either location) Moisture Sensitivity *For additional marking information, refer to Level 1 for SOIC8 Application Note AND8002/D. Level 3 for TSSOP8 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 0.125 in, ORDERING INFORMATION Oxygen Index: 28 to 34 Device Package Shipping Transistor Count = 69 Devices MC100LVEL05DG SOIC8 98 Units/Tube These Devices are Pb-Free, Halogen Free and are RoHS Compliant (Pb-Free) MC100LVEL05DR2G SOIC8 2500/Tape & Reel (Pb-Free) MC100LVEL05DTR2G TSSOP8 2500/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 6 MC100LVEL05/DMC100LVEL05 Table 1. PIN DESCRIPTION PIN FUNCTION D 1 8 V 0 CC D0, D0 D1, D1 ECL Data Inputs Q, Q ECL Data Outputs D 2 7 Q 0 V Positive Supply CC V Negative Supply EE D 3 6 Q 1 D45 V 1 EE Figure 1. Logic Diagram and Pinout Assignment Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Psower Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 41 to 44 5% C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2