MC100LVEL37
3.3 V ECL 1:4 1/2 Clock
Fanout Buffer
Description
The MC100LVEL37 is a fully differential 1:4 fanout buffer. The
device offers two outputs at 1 of the input frequency, and two outputs
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at 2 of the input frequency. The Low Output-Output Skew of the
device makes it ideal for distributing 1x and 1/2x frequency
synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the CLKn input will pull down to V , The CLKn input
EE
will bias around V /2 and the Qn output will go LOW.
CC
SOIC20 WB
DW SUFFIX
CASE 751D05
Features
700 ps Typical Propagation Delays
50 ps Maximum Output-Output Skews
ESD Protection: MARKING DIAGRAM*
> 2 kV Human Body Model
20
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
100LVEL37
PECL Mode Operating Range: V = 3.0 V to 3.8 V
CC
AWLYYWWG
with V = 0 V
EE
NECL Mode Operating Range: V = 0 V
CC
with V = 3.0 V to 3.8 V 1
EE
Internal Input Pulldown Resistors
A = Assembly Location
Qn Output will Default LOW with Inputs Open or at V
EE
WL = Wafer Lot
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
YY = Year
WW = Work Week
Moisture Sensitivity: Level 3 (Pb-Free)
G = Pb-Free Package
(For Additional Information, see Application Note AND8003/D)
Flammability Rating: UL 94 V0 @ 0.125 in, *For additional marking information, refer to
Application Note AND8002/D.
Oxygen Index 28 to 34
Transistor Count = 256 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
ORDERING INFORMATION
Device Package Shipping
MC100LVEL37DWG SOIC20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL37DWR2G SOIC20 WB 1000Tape & Reel
(Pb-Free)
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 7 MC100LVEL37/DMC100LVEL37
V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V
EE CC Table 1. TRUTH TABLE
20 19 18 17 16 15 14 13 12 11
Clk_Sel MR Q0, 1 Q2, 3
L L CLK0/1 CLK0/2
1 2
H L CLK1/1 CLK1/2
X H L L
X = Dont Care
1 2 345 67 9
8 10
Table 2. PIN DESCRIPTION
V V CLK0 CLK0 Clk_Sel CLK1 CLK1 MR V V
CC CC EE EE
PIN FUNCTION
Figure 1. 20-Lead Pinout (Top View)
Q0, Q0; Q1, Q1 ECL Differential Clock 1 Outputs
Q2, Q2; Q3, Q3 ECL Differential Clock 2 Outputs
Warning: All V and V pins must be externally connected
CC EE
to Power Supply to guarantee proper operation.
CLKn, CLKn ECL Differential Clock Inputs
Clk_Sel ECL Input Clock Selection
MR ECL Asynchronous Master Reset
V Positive Supply
CC
V Negative Supply
EE
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V PECL Mode Power Supply V = 0 V 8 to 0 V
CC EE
V NECL Mode Power Supply V = 0 V 8 to 0 V
EE CC
V PECL Mode Input Voltage V = 0 V V V 6 to 0 V
I EE I CC
NECL Mode Input Voltage V = 0 V V V 6 to 0
CC I EE
I Output Current Continuous 50 mA
out
Surge 100
T Operating Temperature Range 40 to +85 C
A
T Storage Temperature Range 65 to +150 C
stg
Thermal Resistance (Junction to Ambient) 0 lfpm SOIC20 WB 90 C/W
JA
500 lfpm SOIC20 WB 60
Thermal Resistance (Junction to Case) Standard Board SOIC20 WB 30 to 35 C/W
JC
T Wave Solder (Pb-Free) < 2 to 3 sec @ 260C 265 C
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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