3.3/5 VECL Differential Phase-Frequency Detector MC100LVEL40 Description The MC100LVEL40 is a three state phase frequencydetector intended for phaselocked loop applications which require a minimum www.onsemi.com amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V power supply. 20 When the reference (R) and the feedback (FB) inputs are unequal in 1 frequency and/or phase the differential up (U) and down (D) outputs SO20 will provide pulse streams which when subtracted and integrated DW SUFFIX provide an error voltage for control of a VCO. CASE 751D The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB MARKING DIAGRAM V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC 20 to 0.5 mA. When not used, V should be left open. BB For application information, refer to AND8040/D, Phase Lock Loop Operation. 100LVEL40 AWLYYWWG The 100 Series Contains Temperature Compensation. Features 1 250 MHz Typical Bandwidth PECL Mode Operating Range: V = 3.0 V to 5.5 V with V = 0 V CC EE A = Assembly Location WL = Wafer Lot NECL Mode Operating Range: YY = Year V = 0 V with V = 3.0 V to 5.5 V CC EE WW = Work Week Internal Input Pulldown Resistor G = PbFree Package This Devices are PbFree, Halogen Free and are RoHS Compliant *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping 38 Units / Tube MC100LVEL40DWG SOIC20 (PbFree) Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: March, 2021 Rev. 11 MC100LVEL40/DMC100LVEL40 Table 1. PIN DESCRIPTION NC V UU V DD V NC NC CCO EE CCO PIN FUNCTION 20 19 18 17 16 15 14 13 12 11 U, U ECL Up Differential Outputs D, D ECL Down Differential Outputs FB, FB ECL Feedback Differential Inputs R, R ECL Reference Differential Inputs V Reference Voltage Output BB V , V Positive Supply CC CCO V Negative Supply EE 1 2 3 4567 8 9 10 NC No Connect NC NC R R V FB FB V NC NC BB CC Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. 20 Lead Pinout (Top View) RU SQ R U R V BB V EE D D R FB SQ FB Figure 2. Logic Diagram Table 2. ATTRIBUTES Characteristics Value ESD Protection Human Body Model > 2 kV Moisture Sensitivity (Note 1) PbFree Pkg SOIC20 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 356 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2