MC100LVEL51 3.3 VECL Differential Clock D FlipFlop Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from www.onsemi.com a3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3 V V . CC 8 The reset input is an asynchronous, level triggered signal. Data enters 8 1 the master portion of the flip-flop when the clock is LOW and is 1 transferred to the slave, and thus the outputs, upon a positive transition of SOIC8 NB TSSOP8 DFN8 the clock. The differential clock inputs of the LVEL51 allow the device to D SUFFIX DT SUFFIX MN SUFFIX be used as a negative edge triggered flip-flop. CASE 751 CASE 948R CASE 506AA The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V and the CLK input will be biased at V /2. EE CC MARKING DIAGRAMS* Features 8 8 475 ps Propagation Delay KVL51 KV51 2.8 GHz Toggle Frequency ALYW ALYW ESD Protection: > 4 kV Human Body Model, 14 1 1 > 200 V Machine Model SOIC8 TSSOP8 DFN8 The 100 Series Contains Temperature Compensation A = Assembly Location PECL Mode Operating Range: V = 3.0 V to 3.8 V CC L = Wafer Lot with V = 0 V EE Y = Year NECL Mode Operating Range: V = 0 V CC W = Work Week with V = 3.0 V to 3.8 V M = Date Code EE = Pb-Free Package Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test (Note: Microdot may be in either location) Moisture Sensitivity Level *For additional marking information, refer to Application Note AND8002/D. Level 1 for SOIC8 NB Level 3 for TSSOP8 Level 1 for DFN8 For Additional Information, see Application Note AND8003/D ORDERING INFORMATION Flammability Rating: UL 94 V0 0.125 in, Device Package Shipping Oxygen Index: 28 to 34 MC100LVEL51DG SOIC8 NB 98 Units/Tube Transistor Count = 114 devices (Pb-Free) These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC100LVEL51DR2G SOIC8 NB 2500/Tape & Reel (Pb-Free) MC100LVEL51DTG TSSOP8 100 Units/Tube (Pb-Free) MC100LVEL51DTR2G TSSOP8 2500/Tape & Reel (Pb-Free) MC100LVEL51MNR4G DFN8 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 7 MC100LVEL51/D 4G M MC100LVEL51 R 1 8 V CC R D 2 D 7 Q Flip-Flop CLK 3 6 Q CLK45 V EE Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE D R CLK Q PIN FUNCTION L L Z L CLK, CLK ECL Differential Clock Input H L Z H Q, Q ECL Differential Output X H X L D ECL D Input Z = LOW to HIGH Transition R ECL Reset Input X = Dont Care V Positive Supp y CC V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Elec- trically connect to the most negative supply (GND) or leave unconnected, floating open. www.onsemi.com 2