MC100LVEL92 5 VTriple PECL Input to LVPECL Output Translator Description The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates www.onsemi.com them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The V supply is to be CC connected to the standard 5 V PECL supply, the LV supply is to be CC connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the V and LV should be bypassed CC CC to ground with 0.01 F capacitors. SOIC20 WB The PECL V pin, an internally generated voltage supply, is BB DW SUFFIX available to this device only. For single-ended input conditions, the CASE 751D unused differential input is connected to V as a switching reference BB voltage. V may also rebias AC coupled inputs. When used, BB decouple V and V via a 0.01 F capacitor and limit current BB CC MARKING DIAGRAM* sourcing or sinking to 0.5mA. When not used, V should be BB left open. 20 Features 500 ps Propagation Delays 100LVEL92 AWLYYWWG 5 V and 3.3 V Supplies Required ESD Protection: Human Body Model > 2 kV, Machine Model > 200 V 1 The 100 Series Contains Temperature Compensation LVPECL Operating Range: LV = 3.0 V to 3.8 V A = Assembly Location CC WL = Wafer Lot PECL Operating Range: V = 4.5 V to 5.5 V CC YY = Year Internal Input Pulldown Resistors WW = Work Week G = Pb-Free Package Q Output will Default LOW with Inputs Open or < GND + 1.3 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test *For additional marking information, refer to Application Note AND8002/D. Moisture Sensitivity: Level 3 (PbFree) For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 0.125 in, ORDERING INFORMATION Oxygen Index 28 to 34 Transistor Count = 247 devices Device Package Shipping These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC100LVEL92DWG SOIC20 WB 38 Units/Tube (Pb-Free) MC100LVEL92DWR2G SOIC20 WB 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 13 MC100LVEL92/DMC100LVEL92 V Q0 Q0 LV Q1 Q1 LV Q2 Q2 V CC CC CC CC Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION LVPECL LVPECL LVPECL Dn, Dn PECL Inputs Qn, Qn LVPECL Outputs PECL V PECL Reference Voltage Output BB LV LVPECL Power Supply CC PECL PECL PECL V PECL Power Supply CC GND Common Ground Rail 1 2 3 4 567 8 9 10 V D0 D0 D1 D1 D2 D2 GND CC Warning: All V , LV , and GND pins must be externally connected CC CC to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: SO20 WB (Top View) Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Power Supply GND = 0 V 8 to 0 V CC LV LVPECL Power Supply GND = 0 V 8 to 0 V CC V PECL Input Voltage GND = 0 V V V 6 to 0 V I I CC I Output Current Continuous 50 mA out Surge 100 I PECL V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 V PECL BB V PECL BB