MC100LVEL91 3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator Description www.onsemi.com The MC100LVEL91 is a triple LVPECL input to ECL output translator. The device receives low voltage differential PECL signals, determined by the V supply level, and translates them to differential CC 3.3 V to 5.0 V ECL output signals. To accomplish the level translation the LVEL91 requires three power rails. The V supply should be connected to the positive CC SOIC20 WB supply, and the V pin should be connected to the negative power EE DW SUFFIX supply. The GND pins are connected to the system ground plane. Both CASE 751D V and V should be bypassed to ground via 0.01 F capacitors. EE CC Under open input conditions, the D input will be biased at V /2 CC MARKING DIAGRAM* and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability. 20 The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused MC100LVEL91 differential input is connected to V as a switching reference voltage. AWLYYWWG BB V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC 1 to 0.5 mA. When not used, V should be left open. BB A = Assembly Location Features WL = Wafer Lot 620 ps Typical Propagation Delay YY = Year WW = Work Week The 100 Series Contains Temperature Compensation G = Pb-Free Package Operating Range: V = 3.8 V to 3.0 V CC V = 3.0 V to 5.5 V GND = 0 V EE *For additional marking information, refer to Q Output will Default LOW with Inputs Open or at GND Application Note AND8002/D. These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Device Package Shipping MC100LVEL91DWG SOIC20 WB 38 Units/Tube (Pb-Free) MC100LVEL91DWR2G SOIC20 WB 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 12 MC100LVEL91/DMC100LVEL91 20 19 18 17 16 15 14 13 12 11 Table 1. PIN DESCRIPTION Pin Function ECL ECL ECL PECL/LVPECL Inputs Dn, Dn ECL Outputs Qn, Qn PECL Reference Voltage Output PECL V BB PECL/ PECL/ PECL/ Positive Supply V CC LVPECL LVPECL LVPECL Negative Supply V EE Ground GND 1 2 3 4 5678 9 10 Figure 1. SO20 Pinout (Top View) and Logic Diagram * All V pins are tied together on the die. CC Warning: All V , V , and GND pins must be externally CC EE connected to Power Supply to guarantee proper operation. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 2 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, (Note 1): Level 3 Pb-Free Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 282 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 V CC V CC D0 Q0 Q0 D0 PECL V GND BB D1 Q1 Q1 D1 GND PECL V BB Q2 D2 Q2 D2 V V CC EE