MC100LVEL29 3.3 VECL Dual Differential Data and Clock D FlipFlop with Set and Reset Description www.onsemi.com The MC100LVEL29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100LVEL29 is pin and functionally equivalent to the MC100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V and the D input will SOIC20 WB EE DW SUFFIX bias around V /2. The outputs will go to a defined state, however the CC CASE 751D05 state will be random based on how the flip flop powers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously. MARKING DIAGRAM* The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused 20 differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB 100LVEL29 and V via a 0.01 F capacitor and limit current sourcing or sinking CC AWLYYWWG to 0.5 mA. When not used, V should be left open. BB Features 1 1100 MHz Flip-Flop Toggle Frequency ESD Protection: > 2 kV Human Body Model A = Assembly Location WL = Wafer Lot 580 ps Typical Propagation Delays YY = Year The 100 Series Contains Temperature Compensation WW = Work Week PECL Mode Operating Range: V = 3.0 V to 3.8 V G = Pb-Free Package CC with V = 0 V EE *For additional marking information, refer to NECL Mode Operating Range: V = 0 V Application Note AND8002/D. CC with V = 3.0 V to 3.8 V EE Internal Input Pulldown Resistors ORDERING INFORMATION Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: Level 3 (Pb-Free) Device Package Shipping (For Additional Information, see Application Note AND8003/D) MC100LVEL29DWG SOIC20 WB 38 Units / Tube (Pb-Free) Flammability Rating: UL 94 V0 0.125 in, MC100LVEL29DWR2G SOIC20 WB 1000 Tape & Reel Oxygen Index: 28 to 34 (Pb-Free) Transistor Count = 313 Devices For information on tape and reel specifications, in- These Devices are Pb-Free, Halogen Free and are RoHS Compliant cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 7 MC100LVEL29/DMC100LVEL29 R0 V Q0 Q0 S0 S1 V Q1 Q1 V CC CC EE 20 19 18 17 16 15 14 13 12 11 Q Q Q Q R S S R D CLK D CLK 1 2 3 4 5678 9 10 D0 D0 CLK0 CLK0 V D1 D1 CLK1 CLK1 R1 BB Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION Table 2. TRUTH TABLE D0, D0 D1, D1 ECL Differential Data Inputs R S D CLK Q Q R0, R1 ECL Reset Inputs L L L Z L H CLK0, CLK0 ECL Differential Clock Inputs L L H Z H L CLK1, CLK1 ECL Differential Clock Inputs H L X X L H L H X X H L S0, S1 ECL Set Inputs H H X X Undef Undef Q0, Q0 Q1, Q1 ECL Differential Data Outputs V Reference Voltage Output BB Z = LOW to HIGH Transition V Positive Supply X = Dont Care CC V Negative Supply EE Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC V = 0 V V V 6 to 0 NECL Mode Input Voltage CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm SOIC20 WB 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2