MC74HC573A Octal 3-State Noninverting Transparent Latch HighPerformance SiliconGate CMOS The MC74HC573A is identical in pinout to the LS573. The devices www.onsemi.com are compatible with standard CMOS outputs with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. SOIC20 TSSOP20 The HC573A is identical in function to the HC373A but has the data DW SUFFIX DT SUFFIX inputs on the opposite side of the package from the outputs to facilitate CASE 751D CASE 948E PC board layout. PIN ASSIGNMENT Features OUTPUT ENABLE 1 20 V CC Output Drive Capability: 15 LSTTL Loads D0 2 19 Q0 Outputs Directly Interface to CMOS, NMOS and TTL D1 3 18 Q1 D2 4 17 Q2 Operating Voltage Range: 2.0 to 6.0 V D3 5 16 Q3 Low Input Current: 1.0 A D4 6 15 Q4 In Compliance with the JEDEC Standard No. 7.0 A Requirements D5 7 14 Q5 D6 8 13 Q6 Chip Complexity: 218 FETs or 54.5 Equivalent Gates D7 9 12 Q7 NLV Prefix for Automotive and Other Applications Requiring GND 10 11 LATCH Unique Site and Control Change Requirements AECQ100 ENABLE Qualified and PPAP Capable MARKING DIAGRAMS These Devices are PbFree and are RoHS Compliant 20 20 LOGIC DIAGRAM HC 74HC573A 573A 219 AWLYYWWG ALYW D0 Q0 3 18 D1 Q1 1 1 4 17 D2 Q2 SOIC20 TSSOP20 5 16 NONINVERTING DATA D3 Q3 A = Assembly Location 6 15 INPUTS OUTPUTS WL, L = Wafer Lot D4 Q4 YY, Y = Year 7 14 D5 Q5 WW, W = Work Week 8 13 D6 Q6 G or = PbFree Package 9 12 D7 Q7 (Note: Microdot may be in either location) 11 LATCH ENABLE FUNCTION TABLE PIN 20 = V CC Inputs Output 1 OUTPUT ENABLE PIN 10 = GND Output Latch Enable Enable D Q Design Criteria Value Units LH H H LH L L Internal Gate Count* 54.5 ea. L L X No Change Internal Gate Progation Delay 1.5 ns HX X Z X = Dont Care Internal Gate Power Dissipation 5.0 W Z = High Impedance Speed Power Product 0.0075 pJ ORDERING INFORMATION *Equivalent to a twoinput NAND gate. See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: May, 2018 Rev. 17 MC74HC573A/DMC74HC573A MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V CC due to high static voltages or electric V DC Input Voltage (Referenced to GND) 0.5 to V + 0.5 V in CC fields. However, precautions must V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V out CC be taken to avoid applications of any I DC Input Current, per Pin 20 mA voltage higher than maximum rated in voltages to this highimpedance cir- I DC Output Current, per Pin 35 mA out cuit. For proper operation, V and in I DC Supply Current, V and GND Pins 75 mA CC CC V should be constrained to the out P Power Dissipation in Still Air, SOIC Package 500 mW range GND (V or V ) V . D in out CC TSSOP Package 450 Unused inputs must always be tied to an appropriate logic voltage T Storage Temperature 65 to +150 C stg level (e.g., either GND or V ). CC T Lead Temperature, 1 mm from Case for 10 Seconds C L Unused outputs must be left open. (TSSOP or SOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: 7 mW/ C from 65 to 125 C TSSOP Package: 6.1 mW/C from 65 to 125 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 2.0 6.0 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V in out CC T Operating Temperature, All Package Types 55 +125 C A t , t Input Rise and Fall Time V = 2.0 V 0 1000 ns r f CC (Figure 1) V = 4.5 V 0 500 CC V = 6.0 V 0 400 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit 55 to V CC 25 C V 85 C 125 C Symbol Parameter Test Conditions Unit V Minimum HighLevel Input Voltage V = 0.1 V or V 0.1 V 2.0 1.5 1.5 1.5 V IH out CC I 20 A 3.0 2.1 2.1 2.1 out 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 V Maximum LowLevel Input Voltage V = 0.1 V or V 0.1 V 2.0 0.5 0.5 0.5 V IL out CC I 20 A 3.0 0.9 0.9 0.9 out 4.5 1.35 1.35 1.35 6.0 1.8 1 8 1.8 V = V or V 2.0 1.9 1.9 1.9 V Minimum HighLevel Output V OH in IH IL 4.5 4.4 4.4 4.4 Voltage I 20 A out 6.0 5.9 5.9 5.9 V = V or V I 2.4mA 3.0 2.48 2.34 2.2 in IH IL out I 6.0 mA 4.5 3.98 3.84 3.7 out I 7.8 mA 6.0 5.48 5.34 5.2 out V Maximum LowLevel Output V = 0.1 V or V 0.1 V 2.0 0.1 0.1 0.1 V OL out CC Voltage I 20 A 4.5 0.1 0.1 0.1 out 6.0 0.1 0.1 0.1 V = V or V I 2.4mA 3.0 0.26 0.33 0.4 in IH IL out I 6.0 mA 4.5 0.26 0.33 0.4 out I 7.8 mA 6.0 0.26 0.33 0.4 out I Maximum Input Leakage Current V = V or GND 6.0 0.1 1.0 1.0 A in in CC I Maximum ThreeState Leakage Output in HighImpedance State 6.0 0.5 5.0 10 A OZ Current V = V or V in IL IH V = V or GND out CC I Maximum Quiescent Supply V = V or GND 6.0 4.0 40 160 A CC in CC Current (per Package) II I = 0 A out www.onsemi.com 2