MM74HC74AN ON Semiconductor

MM74HC74A Dual D-Type Flip-Flop with Preset and Clear February 2008 MM74HC74A Dual D-Type Flip-Flop with Preset and Clear Features General Description Typical propagation delay: 20ns The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the Wide power supply range: 2V6V equivalent LS-TTL part. It possesses the high noise Low quiescent current: 40A maximum (74HC Series) immunity and low power consumption of standard Low input current: 1A maximum CMOS integrated circuits, along with the ability to drive Fanout of 10 LS-TTL loads 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output dur- ing the positive-going transition of the clock pulse. Pre- set and clear are independent of the clock and accomplished by a low level at the appropriate input. The 74HC logic family is functionally and pinout compat- ible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by inter- nal diode clamps to V and ground. CC Ordering Information Package Order Number Number Package Description MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0MM74HC74A Dual D-Type Flip-Flop with Preset and Clear Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H (1) (1) LL X X H H HH HH L HH LL H 0 HH L X Q0 Q Note: Q0 = the level of Q before the indicated input conditions were established. 1. This configuration is nonstable that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level. Top View Logic Diagram 1983 Fairchild Semiconductor Corporation www.fairchildsemi.com MM74HC74A Rev. 1.3.0 2