NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT 1/2/4/8, 2/4/8/16 Clock Divider NB6L239 MR SELA0 SELA1 V CC 16 15 14 13 1 12 QA VT 11 CLK 2 QA NB6L239 CLK 3 10 QB V 4 9 QB BBAC 5 678 EN SELB0 SELB1 V EE Exposed Pad (EP) Figure 2. Pinout: QFN16 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VT Internal 100 CenterTapped Termination Pin for CLK and CLK. 2 CLK LVPECL, CML, LVDS, Noninverted Differential CLOCK Input. HCSL, HSTL Input 3 CLK LVPECL, CML, LVDS, Inverted Differential CLOCK Input. HCSL, HSTL Input 4 V Output Voltage Reference for Capacitor Coupled Inputs, Only. BBAC 5 EN* LVCMOS/LVTTL Input Synchronous Output Enable 6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin 7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin 8 V Power Supply Negative Supply Voltage EE 9 QB LVPECL Output Inverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 10 QB LVPECL Output Noninverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 11 QA LVPECL Output Inverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 12 QA LVPECL Output Noninverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 13 V Power Supply Positive Supply Voltage. CC 14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin 15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin 16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW EP Power Supply (OPT) The Exposed Pad on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to V on the PC board. EE *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.