NB7L72M 2.5V / 3.3V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator www.onsemi.com MultiLevel Inputs w/ Internal Termination MARKING DIAGRAM* Description The NB7L72M is a high bandwidth, low voltage, fully differential NB7L QFN16 2 x 2 crosspoint switch with CML outputs. The NB7L72M design is 72M MN SUFFIX ALYW optimized for low skew and minimal jitter as it produces two identical CASE 485G 1 copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber A = Assembly Location Channel, Backplane and other clock/data distribution applications. L = Wafer Lot The differential IN/IN inputs incorporate internal 50 termination Y = Year W = Work Week resistors and will accept LVPECL, CML, or LVDS logic levels (see = PbFree Package Figure 11). The 16 mA differential CML outputs provide matching (Note: Microdot may be in either location) internal 50 terminations and produce 400 mV output swings when externally terminated with a 50 resistor to V (see Figure 9). *For additional marking information, refer to CC Application Note AND8002/D. The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and is offered in a low profile 3x3 mm 16pin QFN package. Application notes, models, and support documentation are available at + www.onsemi.com. SEL0 The NB7L72M is a member of the GigaComm family of high performance clock products. IN0 Features Q0 VT0 Maximum Input Data Rate > 10 Gb/s IN0 Data Dependent Jitter < 10 ps pkpk Q0 Maximum Input Clock Frequency > 7 GHz Random Clock Jitter < 0.5 ps RMS, Max 0 150 ps Typical Propagation Delay 1 30 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV peaktopeak, typical Operating Range: V = 2.375 V to 3.6 V with GND = 0 V CC Q1 IN1 Internal 50 Input Termination Resistors VT1 QFN16 Package, 3mm x 3mm Q1 + IN1 40C to +85C Ambient Operating Temperature 0 These are PbFree Devices SEL1 Figure 1. Logic Diagram 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2017 Rev. 4 NB7L72M/DNB7L72M Exposed Pad (EP) VT0 SEL0 GND VCC Table 1. INPUT/OUTPUT SELECT TRUTH TABLE 16 15 14 13 SEL0* SEL1* Q0 Q1 L L IN0 IN0 IN0 1 12 Q0 L H IN0 IN1 IN0 2 11 Q0 H L IN1 IN0 NB7L72M H H IN1 IN1 IN1 Q1 3 10 *Defaults HIGH when left open IN1 Q1 4 9 56 7 8 VT1 SEL1 GND VCC Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IN0 LVPECL, CML, Noninverted Differential Input. (Note 1) LVDS Input 2 IN0 LVPECL, CML, Inverted Differential Input. (Note 1) LVDS Input 3 IN1 LVPECL, CML, Inverted Differential Input. (Note 1) LVDS Input 4 IN1 LVPECL, CML, Noninverted Differential Input. (Note 1) LVDS Input 5 VT1 Internal 50 Termination Pin for IN1 and IN1. 6 SEL1 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth Table pin defaults HIGH when left open. 7 GND Negative Supply Voltage 8 VCC Positive Supply Voltage 9 Q1 CML Output Noninverted Differential Output. (Note 1) 10 Q1 CML Output Inverted Differential Output. (Note 1) 11 Q0 CML Output Inverted Differential Output. (Note 1) 12 Q0 CML Output Noninverted Differential Output. (Note 1) 13 VCC Positive Supply Voltage 14 GND Negative Supply Voltage 15 SEL0 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth Table pin defaults HIGH when left open. 16 VT0 Internal 50 Termination Pin for IN0 and IN0 EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2