NC7WZ126L8X ON Semiconductor

TinyLogic UHS Dual Buffer with 3-STATE Outputs NC7WZ126 Description The NC7WZ126 is a Dual Non Inverting Buffer with independent active HIGH enables for the 3STATE outputs. The Ultra High Speed www.onsemi.com device is fabricated with advanced CMOS technology to achieve superior switching performance with high output drive while MARKING maintaining low static power dissipation over a broad V operating CC DIAGRAMS range. The device is specified to operate over the 1.65 V to 5.5 V V CC operating range. The inputs and outputs are high impedance when UQFN8 T6KK V is 0 V. Inputs tolerate voltages up to 5.5 V independent of V CC CC 1.6X1.6, 0.5P XYZ operating range. Outputs tolerate voltages above V when in the CC CASE 523AY 3STATE condition. Features Space Saving US8 Surface Mount Package WZ26 MicroPak PbFree Leadless Package US8 ALYW CASE 846AN Ultra High Speed: t 2.6 ns Typ. into 50 pF at 5 V V PD CC High Output Drive: 24 mA at 3 V V CC Broad V Operating Range: 1.65 V to 5.5 V CC Matches the Performance of LCX when Operated at 3.3 V V CC T6, WZ26 = Specific Device Code Power Down High Impedance Inputs / Outputs KK = 2Digit Lot Run Traceability Code Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation XY = 2Digit Date Code Format Z = Assembly Plant Code Outputs are Overvoltage Tolerant in 3STATE Mode A = Assembly Site Patented Noise / EMI Reduction Circuitry Implemented L = Wafer Lot Number YW = Assembly Start Week These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 6 of this data sheet. A 1 1 Y 1 OE EN 1 A 2 1 Y 2 OE EN 2 Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: October, 2020 Rev. 2 NC7WZ126/DNC7WZ126 Connection Diagrams OE A Y 1 1 2 7 6 5 OE 1 8 V 1 CC A 2 7 OE 1 2 V 8 4 GND CC Y 3 6 Y 2 1 1 2 3 GND45 A 2 OE Y A 2 1 2 Figure 2. Connection Diagram Figure 3. Pad Assignments for MicroPak (Top View) (Top Thru View) PIN DESCRIPTIONS FUNCTION TABLE Pin Names Description Inputs Output OE Enable Inputs for 3STATE Outputs OE A Y n n n A Inputs H L L n Y 3STATE Outputs H H H n L L Z L H Z H = HIGH Logic Level L = LOW Logic Level Z = 3STATE www.onsemi.com 2