DATA SHEET www.onsemi.com Automotive Grade 8 1 Non-Synchronous Boost SOIC8 Controller D SUFFIX CASE 751 NCV8871 MARKING DIAGRAM The NCV8871 is an adjustable output nonsynchronous boost controller which drives an external Nchannel MOSFET. The device 8 uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate 8871xxG ALYW driver. Protection features include internallyset softstart, undervoltage 1 lockout, cyclebycycle current limiting, hiccupmode shortcircuit protection and thermal shutdown. 8871xxG = Specific Device Code Additional features include low quiescent current sleep mode and xx = 00, 03, 04, 05 externallysynchronizable switching frequency. A = Assembly Location L = Wafer Lot Features Y = Year Peak Current Mode Control with Internal Slope Compensation W = Work Week = PbFree Package 1.2 V 2% Reference voltage Fixed Frequency Operation Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump PIN CONNECTIONS Input Undervoltage Lockout (UVLO) Internal SoftStart 1 8 Low Quiescent Current in Sleep Mode EN/SYNC VFB CyclebyCycle Current Limit Protection 2 ISNS 7 VC HiccupMode Overcurrent Protection (OCP) 3 GND 6 VIN HiccupMode ShortCircuit Protection (SCP) 4 GDRV 5 VDRV Thermal Shutdown (TSD) NCV Prefix for Automotive and Other Applications Requiring (Top View) Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable ORDERING INFORMATION This is a PbFree Device Device Package Shipping NCV887100D1R2G SOIC8 2500 / Tape & (PbFree) Reel NCV887103D1R2G SOIC8 2500 / Tape & (PbFree) Reel NCV887104D1R2G SOIC8 2500 / Tape & (PbFree) Reel SOIC8 2500 / Tape & NCV887105D1R2G (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 17 NCV8871/DNCV8871 V g VIN 6 TEMP C L VDRV g C DRV FAULT D VDRV LOGIC 5 V o CLK EN/ EN/SYNC OSC GDRV Q 1 DRIVE 4 SYNC LOGIC SC ISNS 2 C o CL R CSA SNS GND VC 7 3 + R SCP R F1 C VFB 8 C C Gm R F2 SS V ref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin Symbol Pin No. Function 1 EN/SYNC Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable timeout period. 2 ISNS Current sense input. Connect this pin to the source of the external NMOSFET, through a currentsense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally regulated supply for driving the external N MOSFET, sourced from VIN. Bypass with a 1.0 F ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi- tion to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. www.onsemi.com 2 PWM