NLV74HC540ADTR2G ON Semiconductor

MC74HC540A Octal 3-State Inverting Buffer/Line Driver/Line Receiver HighPerformance SiliconGate CMOS MC74HC540A MAXIMUM RATINGS Symbol Parameter Value Unit V DC Supply Voltage 0.5 to +7.0 V CC V DC Input Voltage 0.5 to V + 0.5 V I CC V DC Output Voltage (Note 1) 0.5 V V + 0.5 V O O CC I DC Input Diode Current 20 mA IK I DC Output Diode Current 35 mA OK I DC Output Sink Current 35 mA O I DC Supply Current per Supply Pin 75 mA CC I DC Ground Current per Ground Pin 75 mA GND T Storage Temperature Range 65 to +150 C STG T Lead Temperature, 1 mm from Case for 10 Seconds 260 C L T Junction Temperature Under Bias +150 C J Thermal Resistance SOIC 96 C/W JA TSSOP 128 P Power Dissipation in Still Air at 85 C SOIC 500 mW D 450 TSSOP MSL Moisture Sensitivity Level 1 F Flammability Rating Oxygen Index: 30% 35% UL 94 V0 0.125 in R V ESD Withstand Voltage Human Body Model (Note 2) > 2000 V ESD Machine Model (Note 3) > 200 Charged Device Model (Note 4) > 1000 I Latchup Performance Above V and Below GND at 85 C (Note 5) 300 mA LATCHUP CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. I absolute maximum rating must be observed. O 2. Tested to EIA/JESD22A114A. 3. Tested to EIA/JESD22A115A. 4. Tested to JESD22C101A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 2.0 6.0 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V in out CC T Operating Temperature, All Package Types 55 +125 C A t , t Input Rise and Fall Time (Figure 3) V = 2.0 V 0 1000 ns r f CC V = 4.5 V 0 500 CC V = 6.0 V 0 400 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Unused inputs may not be left open. All inputs must be tied to a high or lowlogic input voltage level.