P3P623S05A/B and P3P623S09A/B Timing-Safe Peak EMI Reduction IC General Features the CLKIN pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad, internal to the device. Clock distribution with Timing-Safe Peak EMI Reduction Multiple P3P623S05 / P3P623S09 devices can accept Input frequency range: 20MHz - 50MHz the same input clock and distribute it. In this case, the skew between the outputs of the two devices is Multiple low skew Timing-safe Outputs: guaranteed to be less than 700pS. P3P623S05: 5 Outputs P3P623S09: 9 Outputs All outputs have less than 200pS of cycle-to-cycle jitter. Supply Voltage: 3.3V0.3V The input and output propagation delay is guaranteed to Packaging Information: be less than 350pS, and the output-to-output skew is P3P623S05: 8 pin TSSOP guaranteed to be less than 250pS. P3P623S09:16 pin TSSOP True Drop-in Solution for Zero Delay Buffer Refer Spread Spectrum Control and Input-Output Skew Table for deviations and Input-Output Skew for Functional Description P3P623S05A/B and P3P623S09A/B devices. P3P623S05/09 is a versatile, 3.3V Zero-delay buffer P3P623S05/09 operates from a 3.3V supply and is designed to distribute Timing-Safe clocks with Peak available in TSSOP package, as shown in the ordering EMI reduction. P3P623S05 is an eight-pin version, information table. accepts one reference input and drives out five low-skew Timing-Safe clocks. P3P623S09 accepts one reference Application input and drives out nine low-skew Timing-Safe clocks. P3P623S05/09 is targeted for use in Displays and All parts have on-chip PLLs that lock to an input clock on memory interface systems. General Block Diagram PLL CLKOUT PLL CLKOUT MUX CLKIN CLKA1 CLK1 CLKIN CLKA2 CLK2 CLKA3 CLK3 CLKA4 P3P623S05A/B CLK4 CLKB1 S2 Select Input Decoding CLKB2 S1 CLKB3 P3P623S09A/B CLKB4 2010 SCILLC. All rights reserved. Publication Order Number: July 2010 Rev. 1 P3P623S05/D P3P623S05A/B and P3P623S09A/B Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves PCBs, etc. These methods are expensive. Spread with a 50% duty cycle and as frequencies increase the spectrum clocking reduces the peak energy by reducing edge rates also get faster. Analysis shows that a square the Q factor of the clock. This is done by slowly wave is composed of fundamental frequency and modulating the clock frequency. The P3P623S05/09 uses harmonics. The fundamental frequency and harmonics the center modulation spread spectrum technique in generate the energy peaks that become the source of which the modulated output frequency varies above and EMI. Regulatory agencies test electronic equipment by below the reference frequency with a specified measuring the amount of peak energy radiated from the modulation rate. With center modulation, the average equipment. In fact, the peak level allowed decreases as frequency is the same as the unmodulated frequency and the frequency increases. The standard methods of there is no performance degradation. reducing EMI are to use shielding, filtering, multi-layer Timing-Safe technology Timing-Safe technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Rev. 1 Page 2 of 11 www.onsemi.com