PEX 8712, PCI Express Gen 3 Switch, 12 Lanes, 3 Ports Highlights The ExpressLane PEX 8712 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX 8712 General Features o 12-lane, 3-port PCIe Gen 3 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 8.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 19 x 19mm , 324-pin FCBGA package o Typical Power: 3.5 Watts storage, communications, and graphics platforms. The PEX 8712 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. PEX 8712 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r3.0 The PEX 8712 employs an enhanced version of PLXs field tested PEX 8612 (compatible w/ PCIe r1.0a/1.1 & 2.0) PCIe switch architecture, which allows users to configure the device in legacy - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant single-host mode or multi-host mode with two host ports capable of 1+1 (one - Supports Access Control Services active & one backup) host failover. This powerful architectural enhancement - Dynamic link-width control enables users to build PCIe based systems to support high-availability, - Dynamic SerDes speed control failover, redundant, or clustered systems. o High Performance performancePAK 9 Read Pacing (bandwidth throttling) High Performance & Low Packet Latency 9 Multicast The PEX 8712 architecture supports packet cut-thru with a maximum 9 Dynamic Buffer/FC Credit Pool latency of 112ns (x4 to x4). This, combined with large packet memory, - Non-blocking switch fabric flexible common buffer/FC credit pool and non-blocking internal switch - Full line rate on all ports - Packet Cut-Thru with 112ns max packet architecture, provides full line rate on all ports for performance-hungry latency (x4 to x4) applications such as servers and switch fabrics. The low latency enables - 2KB Max Payload Size applications to achieve high throughput and performance. In addition to low o Flexible Configuration latency, the device supports a packet payload size of up to 2048 bytes, - Ports configurable as x1, x2, x4, x8 enabling the user to achieve even higher throughput. - Registers configurable with strapping 2 pins, EEPROM, I C, or host software - Lane and polarity reversal Data Integrity - Compatible with PCIe 1.0a PM The PEX 8712 provides end-to-end CRC (ECRC) protection and Poison bit o Multi-Host & Fail-Over Support support to enable designs that require end-to-end data integrity. PLX also - Configurable Non-Transparent (NT) port - Failover with NT port supports data path parity and memory (RAM) error correction circuitry - Two upstream/Host ports with 1+1 throughout the internal data paths as packets pass through the switch. failover to the other upstream port o Quality of Service (QoS) Flexible Configuration - Eight traffic classes per port The PEX 8712s 3 ports can be - Weighted round-robin source x4 x4 port arbitration configured to lane widths of x1, o Reliability, Availability, Serviceability x2, x4, or x8. Flexible buffer visionPAK allocation, along with the device s PEX 8712 PEX 8712 9 Per Port Performance Monitoring flexible packet flow control, Per port payload & header counters maximizes throughput for 9 SerDes Eye Capture 9 PCIe Packet Generator applications where more traffic x4 x4 x2 x2 9 Error Injection and Loopback flows in the downstream, rather x4 - 3 Hot Plug Ports with native HP Signals x4 Gen 2 than upstream, direction. Any 2 - All ports hot plug capable thru I C port can be designated as the (Hot Plug Controller on every port) upstream port, which can be - ECRC and Poison bit support PEX 8712 PEX 8712 NT - Data Path parity changed dynamically. Figure 1 - Memory (RAM) Error Correction shows some of the PEX 8712s x8 Gen 1 - INTA and FATAL ERR signals common port configurations in x4 - Advanced Error Reporting legacy Single-Host mode. Figure 1. Common Port Configurations - Port Status bits and GPIO available Per port error diagnostics - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 5 10/20/2010, Version 1.0 PEX 8712, PCI Express Gen 3 Switch, 12 Lanes, 3 Ports The PEX 8712 can also be configured in Multi-Host mode. redundancy. The PEX 8712 allows the hosts to In Multi-Host mode, a virtual switch is created for each communicate their status to each other via special door- host port and its associated bell registers. In failover mode, if a host fails, the host x4 x4 downstream ports inside the device. designated for failover will disable the upstream port The traffic between the ports of a attached to the failing host and program the downstream virtual switch is completely isolated ports of that host to its own domain. Figure 4a shows a two from the traffic in other virtual host system in Multi-Host mode with two virtual switches PEX 8712 switches. With the PEX 8712 in inside the device and Figure 4b shows Host 1 disabled Multi-Host mode, users can choose after failure and Host 2 having taken over all of Host 1s two ports as host/upstream ports and end-points. x4 assign the remaining downstream Figure 2. Multi-Host port to the desired host. In this Host 1 Host 2 Host 1 Host 2 Port Configuration scenario, one of the hosts will serve as a failover port which will not have a downstream port of PEX 8712 PEX 8712 its own. If the primary host were to fail, the secondary host would then take over this downstream port (see Figure 2). End End Point Point The PEX 8712 also provides several ways to configure its Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over registers. The device can be configured through strapping 2 pins, I C interface, host software, or an optional serial Hot Plug for High Availability EEPROM. This allows for easy debug during the Hot plug capability allows users to replace hardware development phase, performance monitoring during the modules and perform maintenance without powering down operation phase, and driver or software upgrade. the system. The PEX 8712 hot plug capability feature makes it suitable for High Availability (HA) Dual-Host & Failover Support applications. All three ports include a Standard Hot Plug In Single-Host mode, the PEX 8712 supports a Non- Controller. If the PEX 8712 is used in an application Transparent (NT) Port, which enables the where one or more of its downstream ports connect to PCI implementation of dual-host systems for redundancy and Express slots, each ports Hot Plug Controller can be used host failover Primary Host Secondary Host to manage the hot-plug event of its associated slot. Every capability. The NT CPU CPU port on the PEX 8712 is equipped with a hot-plug port allows systems control/status register to support hot-plug capability to isolate host 2 through external logic via the I C interface. memory domains by Root presenting the Complex SerDes Power and Signal Management processor subsystem The PEX 8712 provides low power capability that is fully as an endpoint NT compliant with the PCIe power management specification rather than another PEX 8712 Non-Transparent and supports software control of the SerDes outputs to memory system. Port allow optimization of power and signal strength in a Base address End system. Furthermore, the SerDes block supports loop-back registers are used to Point modes and advanced reporting of error conditions, translate addresses Figure 3. Non-Transparent Port which enables efficient management of the entire system. doorbell registers are used to send interrupts between the address domains Interoperability and scratchpad registers (accessible by both CPUs) allow inter-processor communication (see Figure 3). The PEX 8712 is designed to be fully compliant with the PCI Express Base Specification r2.0, and is backwards compatible to PCI Express Base Specification r1.1 and Multi-Host & Failover Support r1.0a. Additionally, it supports auto-negotiation, lane In Multi-Host mode, PEX 8712 can be configured with reversal, and polarity reversal. Furthermore, the PEX two upstream host ports, each with its own dedicated 8712 is tested for Microsoft Vista compliance. All PLX downstream ports. The device can be configured for 1+1 PLX Technology, www.plxtech.com Page 2 of 5 10/20/2010, Version 1.0