Part Number 856072 140 MHz SAW Filter Data Sheet Features For broadband applications Typical 3dB bandwidth of 33.2 MHz High attenuation Single-ended operation Ceramic Surface Mount Package (SMP) Replaces Sawtek P/N 851937 (BW 3dB=32 MHz) Hermetic RoHS compliant (2002/95/EC), Pb-free Pb Package Pin Configuration Surface Mount 9.00 x 7.01 x 1.50 mm Bottom View SMP-35B 1 2 3 10 4 0.76 1.50 NOM. 1.65 MAX. 9 5 9.00 2.54 8 7 6 1.80 Single-ended Configuration Pin No. Description 4 Output 7.01 2.54 5 Output return 9 Input 10 Input return 1.12 1,2,3,6,7,8 Case ground 1.02 x 2.54 1.02 Dimensions shown are nominal in millimeters All tolerances are 0.15mm except overall length and width +0.10mm/-0.15mm Body: Al O ceramic 2 3 Lid: Kovar, Ni plated Terminations: Au plating 0.5 - 1.0m, over a 2 6m Ni plating Subject to change or obsolescence without notice Rev B 11/07 TriQuint Semiconductor Page 1 of 6 Part Number 856072 140 MHz SAW Filter Data Sheet (1) Electrical Specifications (2) Operating Temperature Range: 0 to +70 C (3) (4) Parameter Minimum Typical Maximum Unit Center Frequency - 140 - MHz Minimum Insertion Loss - 21.7 22.5 dB (5) Lower 1 dB Bandedge - 124.29 125.15 MHz Upper 1 dB Bandedge 154.85 155.88 - (5) Lower 3 dB Bandedge - 123.42 124.2 MHz Upper 3 dB Bandedge 155.8 156.64 - (5) Lower 40 dB Bandedge 119.65 120.31 - MHz Upper 40 dB Bandedge - 159.58 160.35 Amplitude Variation 125.15 - 154.85 MHz - 0.46 1.10 dB p-p Phase Linearity 125.15 - 154.85 MHz - 2.75 6.0 deg p-p Group Delay Variation 125.15 - 154.85 MHz - 15.46 30 ns p-p Absolute Delay - 0.905 - sec (5) Relative Attenuation 15 - 60 MHz 45 56 - dB 60 - 115 MHz 43 54 - dB 165 - 200 MHz 42 52 - dB 200 - 300 MHz 47 58 - dB (6) Terminating Source Impedance: - 50 - (6) Terminating Load Impedance: - 50 - Substrate Material - 128 LiNbO - - 3 o Temperature Coefficient of Frequency - -74 - ppm/ C Notes: 1. All specifications are based on the TriQuint test circuit shown below 2. In production, devices will be tested at room temperature to a guardbanded specification to ensure electrical compliance over temperature 3. Electrical margin has been built into the design to account for the variations due to temperature drift and manufacturing tolerances 4. Typical values are based on average measurements at room temperature 5. Relative to minimum insertion loss 6. This is the optimum impedance in order to achieve the performance shown Test Circuit: Actual matching values may vary due to PCB layout and parasitics 91nH 9 4 50 50 8pF 50 Single-ended 50 Single-ended 1,2,3,5 Output 6,7,8,10 Subject to change or obsolescence without notice Rev B 11/07 TriQuint Semiconductor Page 2 of 6