IDT49FCT3805B 3.3V CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS IDT49FCT3805B BUFFER/CLOCK DRIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT3805B is a 3.3 volt, non-inverting clock driver built using Guaranteed low skew < 500ps (max.) advanced dual metal CMOS technology. The device consists of two banks Very low duty cycle distortion < 1.0ns (max.) of drivers, each with a 1:5 fanout and its own output enable control. The Very low CMOS power levels device has aheartbea monitor for diagnostics and PLL driving. The TTL compatible inputs and outputs MON output is identical to all other outputs and complies with the output Inputs can be driven from 3.3V or 5V components specifications in this document. The FCT3805B offers low capacitance Two independent output banks with 3-state control inputs with hysteresis. 1:5 fanout per bank The FCT3805B is designed for high speed clock distribution where Heartbea monitor output signal quality and skew are critical. The FCT3805B also allows single VCC = 3.3V 0.3V point-to-point transmission line driving in applications such as address Available in SSOP, SOIC, and QSOP packages distribution, where one signal must be distributed to multiple recievers with low skew and high signal quality. For more information on using the FCT3805B with two different input frequencies on bank A and B, please see AN-236. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION VCCA 1 VCCB 20 OEA 2 OA1 19 OB1 5 INA OA1 - OA5 OA2 3 18 OB2 17 OA3 4 OB3 GNDA GNDB 5 16 OA4 6 15 OB4 5 INB OB1 - OB5 OA5 OB5 14 7 OEB GNDQ 13 MON 8 OEB OEA 9 12 MON INA INB 10 11 SOIC/ SSOP/ QSOP TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE MAY 2010 1 c 2005 Integrated Device Technology, Inc. DSC 6879/-IDT49FCT3805B COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS BUFFER/CLOCK DRIVER (1) ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Symbol Description Max Unit Pin Names Description (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V OEA, OEB 3-State Output Enable Inputs (Active LOW) (3) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V INA, INB Clock Inputs (4) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V OAn, OBn Clock Outputs TSTG Storage Temperature 65 to +150 C M O N Monitor Output IOUT DC Output Current 60 to +60 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause (1) FUNCTION TABLE permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational Inputs Outputs sections of this specification is not implied. Exposure to absolute maximum rating OEA, OEB INA, INB OAn, OBn MON conditions for extended periods may affect reliability. 2. VCC terminals. LL L L 3. Input terminals. LHH H 4. Outputs and I/O terminals. HLZ L HH Z H O NOTE: CAPACITANCE (TA = +25 C, f = 1.0MHz) 1. H = HIGH (1) Symbol Parameter Conditions Typ. Max. Unit L = LOW Z = High-Impedance CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. 2