IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE FAST CMOS IDT49FCT805/A BUFFER/CLOCK DRIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The 49FCT805 is a non-inverting buffer/clock driver built using ad- Guaranteed low skew < 700ps (max.) vanced dual metal CMOS technology. Each bank consists of two banks of Low duty cycle distortion < 1ns (max.) drivers. Each bank drives five output buffers from a standard TTL Low CMOS power levels compatible input. These devices feature a heart-beat monitor for TTL compatible inputs and outputs diagnostics and PLL driving. The MON output is identical to all other outputs Rail-to-rail output voltage swing and complies with the output specifications in this document. High drive: -24mA IOH, +64mA IOL The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail Two independent output banks with 3-state control output swing improves noise margin and allows easy interface with CMOS 1:5 fanout per bank inputs. Heartbea monitor output Available in SSOP and SOIC packages FUNCTIONAL BLOCK DIAGRAM OEA 5 INA OA1-OA5 5 INB OB1-OB5 OEB MON The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE MAY 2010 1 c 2006 Integrated Device Technology, Inc. DSC-5836/5IDT49FCT805/A COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE FAST CMOS BUFFER/CLOCK DRIVER (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) 1 20 VTERM Terminal Voltage with Respect to GND 0.5 to +7 V VCCA VCC (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 2 19 OA1 OB1 TSTG Storage Temperature 65 to +150 C 3 18 OA2 OB2 IOUT DC Output Current 60 to +60 mA NOTES: 4 17 OA3 OB3 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation 5 GNDA 16 GNDB of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 6 OA4 conditions for extended periods may affect reliability. 15 OB4 2. Input and VCC terminals. 7 3. Output and I/O terminals. OA5 14 OB5 (1) 8 13 MON NC 9 12 OEA OEB 10 O INA 11 INB CAPACITANCE (TA = +25 C, f = 1.0MHz) (1) Symbol Parameter Conditions Typ. Max. Unit SOIC/ SSOP CIN Input Capacitance VIN = 0V 4.5 6 pF TOP VIEW COUT Output Capacitance VOUT = 0V 5.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Pin 8 is not internally connected on devices with a prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level. PIN DESCRIPTION Pin Names Description OEA, OEB 3-State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAn, OBn Clock Outputs M O N Monitor Output (1) FUNCTION TABLE Inputs Outputs OEA, OEB INA, INB OAn, OBn MON LLL L LH H H HL Z L HH Z H NOTE: 1. H = HIGH L = LOW Z = High-Impedance 2