IDT49FCT806/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE FAST CMOS IDT49FCT806/A BUFFER/CLOCK DRIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT806 is an inverting buffer/clock driver built using advanced dual Guaranteed low skew < 700ps (max.) metal CMOS technology. Each bank consists of two banks of drivers. Each Low duty cycle distortion < 1ns (max.) bank drives five output buffers from a standard TTL compatible input. These Low CMOS power levels devices feature a heart-beat monitor for diagnostics and PLL driving. The TTL compatible inputs and outputs MON output is identical to all other outputs and complies with the output Rail-to-rail output voltage swing specifications in this document. High drive: -24mA IOH, +64mA IOL The FCT806 offers low capacitance inputs and hysteresis. Rail-to-rail Two independent output banks with 3-state control output swing improves noise margin and allows easy interface with CMOS 1:5 fanout per bank inputs. Heartbea monitor output Available in SSOP and SOIC packages FUNCTIONAL BLOCK DIAGRAM OEA 5 INA OA1-OA5 5 INB OB1-OB5 OEB MON The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2010 1 c 2006 Integrated Device Technology, Inc. DSC-5837/3IDT49FCT806/A COMMERCIAL TEMPERATURE RANGE FAST CMOS BUFFER/CLOCK DRIVER (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V VCCA 1 20 VCC (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V OA1 2 19 OB1 TSTG Storage Temperature 65 to +150 C OA2 IOUT DC Output Current 60 to +120 mA 3 18 OB2 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause OA3 4 17 OB3 permanent damage to the device. This is a stress rating only and functional operation GNDA of the device at these or any other conditions above those indicated in the operational 5 16 GNDB sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OA4 6 15 OB4 2. Input and VCC terminals. 3. Output and I/O terminals. OA5 7 14 OB5 (1) NC 8 MON 13 OEA 9 OEB 12 O INA 10 CAPACITANCE (TA = +25 C, f = 1.0MHz) INB 11 (1) Symbol Parameter Conditions Typ. Max. Unit SOIC/ SSOP CIN Input Capacitance VIN = 0V 4.5 6 pF TOP VIEW COUT Output Capacitance VOUT = 0V 5.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Pin 8 is not internally connected on devices with a prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level. PIN DESCRIPTION Pin Names Description OEA, OEB 3-State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAn, OBn Clock Outputs MON Monitor Output (1) FUNCTION TABLE Inputs Outputs OEA, OEB INA, INB OAn, OBn MON LL H H LH L L HL Z H HH Z L NOTE: 1. H = HIGH L = LOW Z = High-Impedance 2