501AMILF Renesas

DATASHEET LOCO PLL CLOCK MULTIPLIER ICS501A Description Features TM The ICS501A LOCO is the most cost effective way to Packaged as 8-pin SOIC (Pb-free) or die generate a high quality, high frequency clock output IDTs lowest cost PLL clock from a lower frequency crystal or clock input. The name Zero ppm multiplication error LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic Input crystal frequency of up to 27 MHz systems. Using Phase-Locked Loop (PLL) techniques, Input clock frequency of up to 50 MHz the device uses a standard fundamental mode, Output clock frequencies up to 200 MHz inexpensive crystal to produce output clocks up to 200 MHz. Extremely low jitter of 25 ps (one sigma) Compatible with all popular CPUs Stored in the chips ROM is the ability to generate nine different multiplication factors, allowing one chip to Duty cycle of 45/55 up to 200 MHz output many common frequencies (see table on page Nine selectable frequencies 2). Operating voltage of 3.3 V The device also has an output enable pin which Tri-state output for board level testing tri-states the clock output when the OE pin is taken low. 25 mA drive capability at TTL levels This product is intended for clock generation. It has low output jitter (variation in the output period), but input to Ideal for oscillator replacement output skew and jitter are not defined or guaranteed. Optimized for output frequencies of up to 200 MHz For applications which require defined input to output (166 MHz maximum for industrial temperature skew, use the ICS570B. version) Industrial temperature version available Advanced, low power CMOS process Block Diagram VDD 2 S1:0 PLL Clock Multiplier X1/ICLK CLK Circuitry Crystal or Crystal and ROM Clock input Oscillator X2 Optional crystal capacitors OE GND IDT LOCO PLL CLOCK MULTIPLIER 1 ICS501A REV H 113011ICS501A LOCO PLL CLOCK MULTIPLIER CLOCK MULTIPLIER Pin Assignment Clock Output Table S1 S0 CLK Minimum Input (MHz) 0 0 4X input 15 X1/ICLK 1 8 X2 0 M 5.333X input 12 VDD 2 7 OE 0 1 5X input 12 M 0 10X input 6 GND 3 6 S0 M M 2X input 30 S1 4 5 CLK M 1 12X input 5 1 0 6X input 10 8 Pin (150 mil) SOIC 1 M 3X input 20 1 1 8X input 10 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 XI/ICLK Input Crystal connection or clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 S1 Tri-level Input Select 1 for output clock. Connect to GND or VDD or float. 5 CLK Output Clock output per table above. 6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. 7 OE Input Output enable. Tri-states CLK output when low. Internal pull-up resistor. 8 X2 Output Crystal connection. Leave unconnected for clock input. IDT LOCO PLL CLOCK MULTIPLIER 2 ICS501A REV H 113011