DATASHEET LOCO PLL CLOCK MULTIPLIER ICS501 Description Features TM The ICS501 LOCO is the most cost effective way to Packaged as 8-pin SOIC, MSOP, or die generate a high-quality, high-frequency clock output from a RoHS 5 (green) or RoHS 6 (green and lead free) lower frequency crystal or clock input. The name LOCO compliant packaging stands for Low Cost Oscillator, as it is designed to replace IDTs lowest cost PLL clock crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a Zero ppm multiplication error standard fundamental mode, inexpensive crystal to Input crystal frequency of 5 - 27 MHz produce output clocks up to 160 MHz. Input clock frequency of 2 - 50 MHz Stored in the chips ROM is the ability to generate nine Output clock frequencies up to 160 MHz different multiplication factors, allowing one chip to output Extremely low jitter of 25 ps (one sigma) many common frequencies (see table on page 2). Compatible with all popular CPUs The device also has an output enable pin which tri-states the clock output when the OE pin is taken low. Duty cycle of 45/55 up to 160 MHz This product is intended for clock generation. It has low Nine selectable frequencies output jitter (variation in the output period), but input to Operating voltage of 3.3 V or 5.0 V output skew and jitter are not defined or guaranteed. For Tri-state output for board level testing applications which require defined input to output skew, use the ICS570B. 25 mA drive capability at TTL levels Ideal for oscillator replacement Industrial temperature version available Advanced, low-power CMOS process Block Diagram VDD 2 S1:0 PLL Clock Multiplier X1/ICLK CLK Circuitry Crystal or Crystal and ROM Clock input Oscillator X2 Optional crystal capacitors OE GND IDT / ICS LOCO PLL CLOCK MULTIPLIER 1 ICS501 REV S 20170331ICS501 LOCO PLL CLOCK MULTIPLIER CLOCKMULTIPLIER Pin Assignment Clock Output Table S1 S0 CLK Minimum Input 0 0 4X input per page 5 X1/ICLK 1 8 X2 0 M 5.3125X input 20 MHz VDD 2 7 OE 0 1 5X input per page 5 M 0 6.25X input 4 MHz GND 3 6 S0 M M 2X input per page 5 S1 4 5 CLK M 1 3.125X input 8 MHz 1 0 6X input per page 5 8 Pin (150 mil) SOIC 1 M 3X input per page 5 1 1 8X input per page 5 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) Common Output Frequency Examples (MHz) Output 20 24 30 32 33.33 37.5 40 48 50 60 62.5 Input 10 12 10 16 16.66 12 10 12 16.66 10 20 Selection (S1, S0) M, M M, M 1, M M, M M, M M, 1 0, 0 0, 0 1, M 1, 0 M, 1 Output 64 66.66 72 75 80 83.33 90 100 106.25 120 125 Input 16 16.66 12 12 10 16.66 15 20 20 15 20 Selection (S1, S0) 0, 0 0, 0 1, 0 M, 0 1, 1 0, 1 1, 0 0, 1 0, M 1, 1 M, 0 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 XI/ICLK Input Crystal connection or clock input. 2 VDD Power Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. 4 S1 Tri-level Iinput Select 1 for output clock. Connect to GND or VDD or float. 5 CLK Output Clock output per table above. 6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. 7 OE Input Output enable. Tri-states CLK output when low. Internal pull-up. 8 X2 Output Crystal connection. Leave unconnected for clock input. IDT / ICS LOCO PLL CLOCK MULTIPLIER 2 ICS501 REV S 20170331