DATASHEET USER CONFIGURABLE CLOCK 5 2 5 -0 1 /0 2 Description Features The ICS525-01/02 are the most flexible way to generate Packaged in 28-pin SSOP (150 mil body) or 28-pin VFQFPN (4x4mm body) a high-quality, high-accuracy, high-frequency clock output from an inexpensive crystal or clock input. The Industrial and commercial versions available in Pb user can configure the device to produce nearly any (lead) free package output frequency from any input frequency by User determines the output frequency by setting all grounding or floating the select pins. Neither internal dividers microcontroller, software, nor device programmer are Eliminates need for custom oscillators needed to set the frequency. Using Phase-Locked Loop No software needed (PLL) techniques, the device accepts a standard Online calculator determines register settings fundamental mode, inexpensive crystal to produce Pull-ups on all select inputs output clocks up to 250MHz. It can also produce a highly accurate output clock from a given input clock, Input crystal frequency of 5 27 MHz keeping them frequency locked together. Input clock frequency of 2 50 MHz Very low jitter For similar capability with a serial interface, use the Duty cycle of 45/55 up to 200MHz 307. For simple multipliers to produce common Operating voltage of 3.0V or 5.5V frequencies, refer to the 50x family of parts, which are Ideal for oscillator replacement smaller and more cost effective. Industrial temperature version available These products are intended for clock generation. They For Zero Delay, refer to the 527 have low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the 527-01. Block Diagram 2 VDD PD X1/ICLK Phase Comparator, CLK Reference Crystal Charge Pump, and VCO Divider Oscillator Crystal or clock Loop Filter Output X2 input Divider VCO Divider Optional crystal capacitors REF 739 2 GND R6:R0 V8:V0 S2:S0 2021 Renesas Electronics Corporation 1 525-01/02 AUGUST 23, 2021525-01/02 USER CONFIGURABLE CLOCK CLOCK MULTIPLIER Pin Assignments R5 1 28 R4 R6 2 27 R3 28 27 26 25 24 23 22 S0 3 26 R2 1 21 R5 CLK S1 4 25 R1 2 20 R6 GND S2 5 24 R0 VDD 6 23 VDD 19 3 S0 PD X1/ICLK 7 22 REF EPAD S1 4 18 V8 X2 8 21 CLK 5 17 S2 V7 GND 9 20 GND 10 19 V0 PD 6 16 V V6 DD V1 11 18 V8 7 X1/CLKIN 15 V5 V2 12 17 V7 8 9 10 11 12 13 14 V3 13 16 V6 V4 14 15 V5 28-pin VFQFPN 28-pin SSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1, 2, R5, R6, I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 24-28 R0-R4 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table on page 3. 6, 23 VDD Power Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal or input clock. 8 X2 X2 Crystal connection. Connect to a crystal or leave unconnected for clock. 9, 20 GND Power Connect to ground. 10 - 18 V0 - V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 PD Input Power-down. Active low. Turns off entire chip when low. Clock outputs tri-stated. 21 CLK Output Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency. 22 REF Output Reference output. Buffered crystal oscillator (or clock ) output. KEY: I(PU) = Input with internal pull-up resistor X1, X2 = crystal connections 2021 Renesas Electronics Corporation 2 525-01/02 AUGUST 23, 2021 X2 R4 GND R3 R2 V0 V1 R1 V2 R0 V3 V DD V4 REF