DATASHEET CLOCK DIVIDER ICS542 Description Features The ICS542 is cost effective way to produce a high-quality 8-pin SOIC package, Pb free clock output divided from a clock input. The chip accepts a Available in RoHS compliant package clock input up to 156 MHz at 3.3 V and produces a divide by IDTs lowest cost clock divider 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. Low skew (500 ps) outputs. One is /2 of the other Easy to use with other generators and buffers For instance, if an 100 MHz input clock is used, the ICS542 can produce low-skew 50 MHz and 25 MHz clocks, or low Input clock frequency up to 156 MHz skew 25 MHz and 12.5 MHz clocks. The chip has an Output clock duty cycle of 45/55 all-chip power-down mode that stops the outputs low, and Power-down turns off chip an OE pin that tri-states the outputs. Output Enable See the ICS541 and ICS543 for other clock dividers, and the ICS501, 502, 511, 512, and 525 for clock multipliers. Advanced, low-power CMOS process Operating voltage of 3.3 V or 5 V Does not degrade phase noise - no PLL Available in industrial and commercial temperature ranges Block Diagram VDD CLK1 S1, S0 Divider and /2 Selection Circuitry CLK2 Input Clock OE (both outputs) GND IDT / ICS CLOCK DIVIDER 1 ICS542 REV J 051310ICS542 CLOCK DIVIDER CLOCK DIVIDER Pin Assignment Clock Decoding Table S1 S0 CLK CLK/2 ICLK 1 8 CLK 00 Power Down All VDD 2 7 CLK/2 0 1 Input/6 Input/12 1 0 Input/8 Input/16 GND 3 6 OE 1 1 Input/2 Input/4 S0 4 5 S1 0 = connect directly to ground 1 = connect directly to VDD 8-pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK XI Clock input. 2 VDD Power Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. Select 0 for output clock. Connect to GND or VDD, per decoding table above. 4 S0 Input Internal pull-up resistor. Select 1 for output clock. Connect to GND or VDD, per decoding table above. 5 S1 Input Internal pull-up resistor. Output Enable. Tri-states both output clocks when low. Internal pull-up 6 OE Input resistor. 7 CLK/2 Output Clock output per table above. Low skew divide by two of pin 8 clock. 8 CLK Output Clock output per table above. External Components Series Termination Resistor PCB Layout Recommendations Clock output traces over one inch should use series For optimum device performance and lowest output phase termination. To series terminate a 50 trace (a commonly noise, the following guidelines should be observed. used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. 1) The 0.01F decoupling capacitor should be mounted on The nominal impedance of the clock output is 20 . the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling Decoupling Capacitor capacitor and VDD pin. The PCB trace to VDD pin should As with any high-performance mixed-signal IC, the ICS542 be kept as short as possible, as should the PCB trace to the must be isolated from system power supply noise to perform ground via. Distance of the ferrite bead and bulk decoupling optimally. from the device is less critical. A decoupling capacitor of 0.01F must be connected 2) To minimize EMI, the 33 series termination resistor (if between VDD and the PCB ground plane. needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the IDT / ICS CLOCK DIVIDER 2 ICS542 REV J 051310