544M-01LF Renesas

DATASHEET CLOCK DIVIDER ICS544-01 Description Features The ICS544-01 is crystal oscillator module IC with Packaged in 8-pin SOIC divide by 512 frequency output. It employs a 16.777216 Pb-free package MHz fundamental frequency crystal source oscillator to IDTs lowest cost clock divider generate 32.768 kHz output crystal oscillator output. In Easy to use with other generators and buffers addition a divide by 256, 64 and 32 options are also Input crystal at 16.777216MHz provided through select pins. The chip has an OE pin Output clock duty cycle of 45/55 that tri-states the output and stops the oscillator circuits. Output Enable TM The ICS544-01 is a member of IDTs ClockBlocks Advanced, low-power CMOS process family of clock building blocks. See the ICS541 and Operating voltage of 2.25 V to 3.6 V ICS542 for other clock dividers, and the ICS501, 502, Does not degrade phase noise - no PLL 511, 512, and 525 for clock multipliers. Available in industrial temperature range Block Diagram VDD S1, S0 (1:0) Divider and Selection CLK1 Circuitry X1 /32, /64 /256, /512, 16.777216MHz crystal input X2 Optional tuning capacitors OE GND IDT CLOCK DIVIDER 1 ICS544-01 REV B 051810ICS544-01 CLOCK DIVIDER CLOCK DIVIDER Pin Assignment Clock Divider Table S1 S0 CLK X1/ICLK 1 8 S1 0 0 Input/32 X2 2 7 VDD 0 1 Input/64 10 Input/256 GND 3 6 OE 11 Input/512 S0 4 5 CLK 0 = connect directly to ground 1 = connect directly to VDD 8-pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 X1/ICLK XI Crystal input. 2 X2 Xo Connect to crystal for crystal input and leave open for clock input. 3 GND Power Connect to ground. Select 0 for output clock. Connect to GND or VDD, per divider table above. 4 S0 Input Internal pull-up resistor. 5 CLK Output Clock output per table above. Internal Pull down resistor. Output Enable.Tri-states output clock when low. Also shuts down the oscillator 6 OE Input circuit. Internal pull-up resistor. OE=1 normal operation. 7 VDD Power Connect to 2.25 V to 3.6 V. Select 1 for output clock. Connect to GND or VDD, per divider table above. 8 S1 Input Internal pull-up resistor. External Components Series Termination Resistor Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS544-01 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane. On chip capacitors connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (C -12)*2 in this equation, L C =crystal load capacitance in pf. For example, for a L crystal with a 16 pF load cap, each external crystal cap would be 8 pF. (16-12)x2 =8. IDT CLOCK DIVIDER 2 ICS544-01 REV B 051810